[RFC] clk: rockchip: Fix CPLL setup issue

[Alexander Shiyan]

Hello.

> On Fri, Sep 26, 2025 at 04:15:14PM +0300, Alexander Shiyan wrote:
> > This is a dirty patch to solve the RK3588 CPLL clock setup issue.
> > It's taken from the Rockchip U-Boot repository [1].
> > Any ideas on how to improve it?
> >
> > [1] https://github.com/rockchip-linux/u-boot/commit/bd11beba4f997b62809d24eba30a8713c8bbeb81
...
> > +     /* Barebox addition */
> > +     if (pll->reg_base - pll->ctx->reg_base == 0x1a0) {
> > +             /* Determine CPLL clock and patch clk_bisrintf_pllsrc_en back */
> > +             writel(HIWORD_UPDATE(0, BIT(1), 0),
> > +                    pll->ctx->reg_base + 0x84c);
> > +     }
>
> Resetting this bit is not in the U-Boot patch you reference. Do we need
> this?

Yes.
https://github.com/rockchip-linux/u-boot/commit/7560cacdd3a68bb475f23b4249a98025c89064d4