RK3588 CPLL question

[Michael Tretter]

Hi,

On Wed, 24 Sep 2025 16:05:02 +0300, Alexander Shiyan wrote:
> There's still no successful result with properly configuring the CPLL
> for the RK3588.
> Without it, kernel startup becomes pointless, as important frequencies
> for network
> interfaces, and likely some others, remain half the speed required for
> system operation.
> The CPLL in U-Boot is programmed for a frequency of 1500 MHz, and it
> works there,
> but in barebox these actions do not bring success.
> 
> CRU_CPLL_CON1 Address: Operational Base + offset (0x01A4)
> CRU_CPLL_CON6 Address: Operational Base + offset (0x01B8)
> CRU_MODE_CON00 Address: Operational Base + offset (0x0280)
> 
> md -l 0xfd7c0280+1
> fd7c0280: 00000545
> 
> md -l 0xfd7c01a0+28
> fd7c01a0: 0000007d 00000081 00000000 00000000
> fd7c01b0: 00000000 00000000 00009c00
> 
> clk_set_parent cpll xin24m
> md -l 0xfd7c0280+1
> fd7c0280: 00000445
> 
> md -l 0xfd7c01a0+28
> fd7c01a0: 0000007d 00002081 00000000 00000000
> fd7c01b0: 00000000 00000000 00004000
> 
> mw -l 0xfd7c01a4 0x20000000
> <Freeze here>
> 
> So the error occurs when the CPLL is turned on. Line:
> writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), pll->reg_base +
> RK3588_PLLCON(1));
> 
> I don't know what else to try...
> Has anyone had any successful experience running a barebox for RK3588
> with working network interfaces?

I have barebox running with working network interfaces on a Radxa ROCK
5T board. I'm not familiar with the clock tree, yet, but on my system,
the CPLL is also set to 750 MHz and child clocks seem to be running at
half their rate.

Michael

> 
> Thanks!
> 
> пн, 7 апр. 2025 г. в 15:31, Alexander Shiyan <eagle.alexander923 at gmail.com>:
> 
> >
> > Hello.
> >
> > Unfortunately, there is still a stupor in this issue
> > Any PLL can be configured normally, except CPLL.
> > Changing CPLL freezes the system. I tried to use some tricks from
> > U-boot, but to no avail...
> >
> > barebox at Diasom DS-RK3588-BTB-EVB:/ clk_set_parent cpll xin24m
> > barebox at Diasom DS-RK3588-BTB-EVB:/ clk_set_rate pll_cpll 816000000
> > rockchip_rk3588_pll_set_rate: changing pll_cpll to 816000000 with a
> > parent rate of 24000000
> > rockchip_rk3588_pll_set_params: rate settings for 816000000 p: 2, m:
> > 272, s: 2, k: 0
> > <freeze here>
> >
> > пт, 4 апр. 2025 г. в 10:29, Sascha Hauer <s.hauer at pengutronix.de>:
> > >
> > > On Thu, Apr 03, 2025 at 05:20:33PM +0300, Alexander Shiyan wrote:
> > > > I found this hack:
> > > > https://github.com/u-boot/u-boot/blob/master/drivers/clk/rockchip/clk_rk3588.c#L1933
> > >
> > > Let's do the same then.
> > >
> > > It would be nicer to have the CPLL setting in the assigned-clock-rates
> > > property. That should be done in the upstream dtsi though, overwriting
> > > the assigned-clock-rates in the barebox dtsi would mean we would have to
> > > copy the many existing settings and hope they don't change upstream.
> > >
> > > Sascha
> > >
> > > >
> > > > чт, 3 апр. 2025 г. в 17:08, Sascha Hauer <s.hauer at pengutronix.de>:
> > > > >
> > > > > On Thu, Apr 03, 2025 at 05:01:05PM +0300, Alexander Shiyan wrote:
> > > > > > Thanks Sascha!
> > > > > >
> > > > > > So something is wrong here.
> > > > > > At least the GMAC0/1 interfaces end up with the wrong frequency.
> > > > > > I have another image with u-boot and Rockchip kernel where CPLL
> > > > > > is 1.5GHz and network is ok.
> > > > >
> > > > > The only place where the PLL rates are configured in barebox is via
> > > > > assigned-clock-rates in the clock controller node. PLL_CPLL doesn't show
> > > > > up there, so I would assume it is just left to the default whatever that
> > > > > is.
> > > > >
> > > > > You could chainload barebox from U-Boot and see what the CPLL rate is
> > > > > then.
> > > > >
> > > > > Sascha