[PATCH 05/11] ARM: dts: socfpga: adapt upstream SA2 device tree

[David Picard]

Signed-off-by: David Picard <david.picard at clermont.in2p3.fr>
---
 arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi | 25 +++++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
index 73bd75fcf224fbf31fce27dda6566d4bfe37d624..52a9d1a6c396fb3df56acbaf99d40594dea19944 100644
--- a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
@@ -9,9 +9,14 @@
 
 #include <arm/intel/socfpga/socfpga_cyclone5.dtsi>
 
+/ {
+	barebox,deep-probe;
+};
+
 / {
 	model = "Enclustra Mercury+ SA2";
-	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+	compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", "altr,socfpga-cyclone5", "altr,socfpga";
+
 
 	chosen {
 		stdout-path = "serial0:115200n8";
@@ -57,7 +62,8 @@ isl12020: rtc at 6f {
 		reg = <0x6f>;
 	};
 
-	atsha204a: crypto at 64 {
+	atsha204a: atsha204a at 64 {
+		status = "okay";
 		compatible = "atmel,atsha204a";
 		reg = <0x64>;
 	};
@@ -125,6 +131,21 @@ mdio0 {
 		phy3: ethernet-phy at 3 {
 			reg = <3>;
 
+			/*
+			Ethernet PHY reset pin (active low, GPIO44) :
+			- 1st field: GPIO controller phandle
+			- 2nd field: GPIO line offset
+			- 3rd field: flags (see gpio.txt)
+
+			Reference:
+			- Cyclone 5 HPS technical reference, table 23-1: GPIO44 is on controller
+			GPIO1, whose 1st line is GPIO29. The offset is thus 44 - 29 = 15.
+			- Linux documentation:
+				- Documentation/devicetree/bindings/gpio/gpio.txt
+				- Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
+			*/
+			reset-gpios = <&portb 15 0x01>;
+
 			/* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
 			rxc-skew-ps = <1680>;
 			rxd0-skew-ps = <420>;

-- 
2.43.0