[PATCH 2/2] ARM: dts: rockchip: Set CPLL frequency for RK3588

[Alexander Shiyan]

Hello Michael.

Here is my frequency dump with a working eMMC chip.
Can you compare with your CLK values?

barebox at Diasom DS-RK3588-BTB-EVB:/ clk_dump -v cclk_emmc
xin24m (rate 24000000, enable_count: 15, enabled)
    pll_gpll (rate 1188000000, enable_count: 1, enabled)
        gpll (rate 1188000000, enable_count: 13, always enabled)
        `---- possible parents: xin24m pll_gpll xin32k
            cclk_emmc (rate 51652174, enable_count: 1, enabled)
            `---- possible parents: gpll cpll xin24m
barebox at Diasom DS-RK3588-BTB-EVB:/ clk_dump -v hclk_emmc
xin24m (rate 24000000, enable_count: 15, enabled)
    pll_gpll (rate 1188000000, enable_count: 1, enabled)
        gpll (rate 1188000000, enable_count: 13, always enabled)
        `---- possible parents: xin24m pll_gpll xin32k
            clk_200m_src (rate 198000000, enable_count: 12, enabled)
            `---- possible parents: gpll cpll
                hclk_nvm_root (rate 198000000, enable_count: 1, enabled)
                `---- possible parents: clk_200m_src clk_100m_src
clk_50m_src xin24m
                    hclk_nvm (rate 198000000, enable_count: 2, enabled)
                        hclk_emmc (rate 198000000, enable_count: 1, enabled)
barebox at Diasom DS-RK3588-BTB-EVB:/ clk_dump -v aclk_emmc
xin24m (rate 24000000, enable_count: 15, enabled)
    pll_cpll (rate 1500000000, enable_count: 1, enabled)
        cpll (rate 1500000000, enable_count: 18, always enabled)
        `---- possible parents: xin24m pll_cpll xin32k
            aclk_nvm_root (rate 300000000, enable_count: 2, enabled)
            `---- possible parents: gpll cpll
                aclk_emmc (rate 300000000, enable_count: 1, enabled)
barebox at Diasom DS-RK3588-BTB-EVB:/ clk_dump -v bclk_emmc
xin24m (rate 24000000, enable_count: 15, enabled)
    pll_cpll (rate 1500000000, enable_count: 1, enabled)
        cpll (rate 1500000000, enable_count: 18, always enabled)
        `---- possible parents: xin24m pll_cpll xin32k
            bclk_emmc (rate 187500000, enable_count: 1, enabled)
            `---- possible parents: gpll cpll
barebox at Diasom DS-RK3588-BTB-EVB:/ clk_dump -v tmclk_emmc
xin24m (rate 24000000, enable_count: 15, enabled)
    tmclk_emmc (rate 24000000, enable_count: 1, enabled)

ср, 1 окт. 2025 г. в 17:06, Michael Tretter <m.tretter at pengutronix.de>:
>
> Hi Alexander,
>
> On Mon, 29 Sep 2025 16:58:57 +0300, Alexander Shiyan wrote:
> > Explicitly configure CPLL frequency to 1500 MHz to ensure system
> > stability and reliable operation.
> > The change aligns with Rockchip's recommended practices for clock
> > configuration in embedded systems using RK3588 SoCs.
>
> This change breaks eMMC operation in barebox on ROCK 5T boards. I get
> the following alert during barebox boot:
>
>         ALERT: rk3568-dwcmshc-sdhci fe2e0000.mmc at fe2e0000.of: DMA wait timed out. Resetting, but recovery unlikely
>         WARNING: mmc0: Card's startup fails with -110
>
> I fumbled a bit with the clocks, especially the aclk_emmc, but no
> improvement so far.
>
> Michael
>
> > Signed-off-by: Alexander Shiyan <eagle.alexander923 at gmail.com>
> > ---
> >  arch/arm/dts/rk3588.dtsi | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
> > index 416700cf0e..42d692a9bd 100644
> > --- a/arch/arm/dts/rk3588.dtsi
> > +++ b/arch/arm/dts/rk3588.dtsi
> > @@ -1,6 +1,9 @@
> >  // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >
> >  / {
> > +     assigned-clocks = <&cru PLL_CPLL>;
> > +     assigned-clock-rates = <1500000000>;
> > +
> >       dmc: memory-controller {
> >               compatible = "rockchip,rk3588-dmc";
> >               rockchip,pmu = <&pmu1grf>;