[PATCH 2/2] ARM: dts: rockchip: Set CPLL frequency for RK3588

[Michael Tretter]

Hi Alexander,

On Mon, 29 Sep 2025 16:58:57 +0300, Alexander Shiyan wrote:
> Explicitly configure CPLL frequency to 1500 MHz to ensure system
> stability and reliable operation.
> The change aligns with Rockchip's recommended practices for clock
> configuration in embedded systems using RK3588 SoCs.

This change breaks eMMC operation in barebox on ROCK 5T boards. I get
the following alert during barebox boot:

	ALERT: rk3568-dwcmshc-sdhci fe2e0000.mmc at fe2e0000.of: DMA wait timed out. Resetting, but recovery unlikely
	WARNING: mmc0: Card's startup fails with -110

I fumbled a bit with the clocks, especially the aclk_emmc, but no
improvement so far.

Michael

> Signed-off-by: Alexander Shiyan <eagle.alexander923 at gmail.com>
> ---
>  arch/arm/dts/rk3588.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
> index 416700cf0e..42d692a9bd 100644
> --- a/arch/arm/dts/rk3588.dtsi
> +++ b/arch/arm/dts/rk3588.dtsi
> @@ -1,6 +1,9 @@
>  // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>  
>  / {
> +	assigned-clocks = <&cru PLL_CPLL>;
> +	assigned-clock-rates = <1500000000>;
> +
>  	dmc: memory-controller {
>  		compatible = "rockchip,rk3588-dmc";
>  		rockchip,pmu = <&pmu1grf>;