[PATCH v2] clk: rockchip rk3588: configure CPLL in driver

[Sascha Hauer]

On Tue, 28 Oct 2025 08:26:25 +0100, Sascha Hauer wrote:
> The rk3588 CPLL should be configured to 1.5GHz and 09c87c85e0 ("ARM:
> dts: rockchip: Set CPLL frequency for RK3588") does this. It does it
> however after the assigned-clocks/assigned-clock-rates properties of the
> "rockchip,rk3588-cru" node have been evaluated which contain a setting
> of CLK_150M_SRC which is a child clock of the CPLL.  Configuring the
> CPLL after CLK_150M_SRC alters the setting of the just configured 150M
> clock again.
> 
> [...]

Applied, thanks!

[1/1] clk: rockchip rk3588: configure CPLL in driver
      https://git.pengutronix.de/cgit/barebox/commit/?id=45b4b47cc650 (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer at pengutronix.de>