[PATCH master] video: IPUv3-LDB: fix LVDS serial clock configuration

[Philipp Zabel]

On Mi, 2025-05-07 at 09:25 +0200, Ahmad Fatoum wrote:
> Hello Sascha,
> 
> On 5/6/25 09:51, Sascha Hauer wrote:
> > On Sun, Apr 27, 2025 at 03:44:53PM +0200, Ahmad Fatoum wrote:
> 
> > > @@ -189,10 +200,10 @@ static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di,
> > >  		pixclk *= 2;
> 
> This multiplication by 2 is only done for the single channel mode.

TBH, I don't quite understand this. In the kernel, di_clk is calculated
as drm_display_mode->clock * 1000 in either mode.

Does this mean that the pixclk parameter passed to imx6q_ldb_prepare
was 3.5 MHz here, resulting in the 7 MHz rate that ldb_di0_podf is set
to after this multiplication?

> > >  
> > >  	if (dual) {
> > > -		imx6q_set_clock(ldb, ipuno, dino, 0, pixclk);
> > > -		imx6q_set_clock(ldb, ipuno, dino, 1, pixclk);
> > > +		imx6q_set_clock(ldb, ipuno, dino, 0, pixclk * 7, pixclk);
> > > +		imx6q_set_clock(ldb, ipuno, dino, 1, pixclk * 7, pixclk);

The di_clk:serial_clk ratio is 1:7 here, regardless of what happened to
pixclk before.

> > I think in dual channel mode we have to maintain a 1:3.5 setting instead
> > of 1:7.
> 
> That means pixclk for dual channel mode here is already half the value
> it would be for single channel, i,e. 1:3.5.

In dual mode, the ipu_di clock has to run at double the serial_clk/7
rate because one IPU DI feeds two LDB channels. That's why the ratio
between ldb_di0/1_sel and ipu1_di0_sel must be set to 1:3.5, and so
that's what the ratio between imx6q_set_clock()'s serial_clk and di_clk
parameters should be as well.

regards
Philipp