RK3588 CPLL question

[Alexander Shiyan]

I found this hack:
https://github.com/u-boot/u-boot/blob/master/drivers/clk/rockchip/clk_rk3588.c#L1933

чт, 3 апр. 2025 г. в 17:08, Sascha Hauer <s.hauer at pengutronix.de>:
>
> On Thu, Apr 03, 2025 at 05:01:05PM +0300, Alexander Shiyan wrote:
> > Thanks Sascha!
> >
> > So something is wrong here.
> > At least the GMAC0/1 interfaces end up with the wrong frequency.
> > I have another image with u-boot and Rockchip kernel where CPLL
> > is 1.5GHz and network is ok.
>
> The only place where the PLL rates are configured in barebox is via
> assigned-clock-rates in the clock controller node. PLL_CPLL doesn't show
> up there, so I would assume it is just left to the default whatever that
> is.
>
> You could chainload barebox from U-Boot and see what the CPLL rate is
> then.
>
> Sascha
>
> --
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |