RK3588 CPLL question

[Sascha Hauer]

On Thu, Apr 03, 2025 at 05:01:05PM +0300, Alexander Shiyan wrote:
> Thanks Sascha!
> 
> So something is wrong here.
> At least the GMAC0/1 interfaces end up with the wrong frequency.
> I have another image with u-boot and Rockchip kernel where CPLL
> is 1.5GHz and network is ok.

The only place where the PLL rates are configured in barebox is via
assigned-clock-rates in the clock controller node. PLL_CPLL doesn't show
up there, so I would assume it is just left to the default whatever that
is.

You could chainload barebox from U-Boot and see what the CPLL rate is
then.

Sascha

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