[PATCH master] openrisc: dts: describe all 4 UARTs

[Ahmad Fatoum]

Starting with QEMU v7.1.0, the openrisc_sim machine features 4 serial
ports. This was introduced with QEMU commit 777784bda468 ("hw/openrisc:
support 4 serial ports in or1ksim"), which also made the last console
(serial at 90000300) the default.

This is still the case as of v9.1.0-rc3, but I submitted a patch to
restore serial at 90000000 as default. Until that's merged, let's just
activate all consoles after describing them in the device tree.

Signed-off-by: Ahmad Fatoum <a.fatoum at pengutronix.de>
---
Optimally, we would start consuming the device tree supplied by QEMU,
but this should be good enough to fix the test suite breakage.
---
 arch/openrisc/configs/generic_defconfig |  1 +
 arch/openrisc/dts/or1ksim.dts           | 21 +++++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/arch/openrisc/configs/generic_defconfig b/arch/openrisc/configs/generic_defconfig
index 1f2d40eae9f7..417ae4db3650 100644
--- a/arch/openrisc/configs/generic_defconfig
+++ b/arch/openrisc/configs/generic_defconfig
@@ -3,6 +3,7 @@ CONFIG_BUILTIN_DTB_NAME="or1ksim"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
+CONFIG_CONSOLE_ACTIVATE_ALL=y
 CONFIG_PARTITION=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
 CONFIG_LONGHELP=y
diff --git a/arch/openrisc/dts/or1ksim.dts b/arch/openrisc/dts/or1ksim.dts
index 7316cc677046..ac938be9ee31 100644
--- a/arch/openrisc/dts/or1ksim.dts
+++ b/arch/openrisc/dts/or1ksim.dts
@@ -43,6 +43,27 @@ serial0: serial at 90000000 {
 		clock-frequency = <50000000>;
 	};
 
+	serial1: serial at 90000100 {
+		compatible = "ns16550a";
+		reg = <0x90000100 0x100>;
+		interrupts = <2>;
+		clock-frequency = <50000000>;
+	};
+
+	serial2: serial at 90000200 {
+		compatible = "ns16550a";
+		reg = <0x90000200 0x100>;
+		interrupts = <2>;
+		clock-frequency = <50000000>;
+	};
+
+	serial3: serial at 90000300 {
+		compatible = "ns16550a";
+		reg = <0x90000300 0x100>;
+		interrupts = <2>;
+		clock-frequency = <50000000>;
+	};
+
 	enet0: ethoc at 92000000 {
 		compatible = "opencores,ethoc";
 		reg = <0x92000000 0x100>;
-- 
2.39.2