[PATCH 1/2] mci: core: check for both 3.3v and 1.8v DDR support

[Ahmad Fatoum]

We don't yet support the higher speed modes that require voltage
switching, so regulator interaction in barebox was so far limited to
enabling the supply. barebox also doesn't keep track what voltage the
eMMC is running on, so it doesn't know whether MMC_CAP_MMC_1_8V_DDR
or MMC_CAP_MMC_3_3V_DDR is the correct bit to check. Let's just accept
either until we add support for higher speed modes. barebox will
fallback to the non-DDR speed mode anyway if it fails to read the
ext_csd using it.

Signed-off-by: Ahmad Fatoum <a.fatoum at pengutronix.de>
---
 drivers/mci/mci-core.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
index 175753cca5d7..07eca96a9d61 100644
--- a/drivers/mci/mci-core.c
+++ b/drivers/mci/mci-core.c
@@ -1289,7 +1289,13 @@ static int mci_mmc_select_hs_ddr(struct mci *mci)
 	struct mci_host *host = mci->host;
 	int ret;
 
-	if (!(mci_caps(mci) & MMC_CAP_MMC_1_8V_DDR))
+	/*
+	 * barebox MCI core does not change voltage, so we don't know here
+	 * if we should check for the 1.8v or 3.3v mode. Until we support
+	 * higher speed modes that require voltage switching like HS200/HS400,
+	 * let's just check for either bit.
+	 */
+	if (!(mci_caps(mci) & (MMC_CAP_MMC_1_8V_DDR | MMC_CAP_MMC_3_3V_DDR)))
 		return 0;
 
 	ret = mci_mmc_try_bus_width(mci, host->bus_width, MMC_TIMING_MMC_DDR52);
-- 
2.39.2