[PATCH v2 32/34] ARM: mmu32: Use pages for early MMU setup

[Sascha Hauer]

On Wed, May 17, 2023 at 04:21:32PM +0200, Ahmad Fatoum wrote:
> On 17.05.23 11:03, Sascha Hauer wrote:
> > Up to now we use 1MiB sections to setup the page tables in PBL. There
> > are two places where this leads to problems. First is OP-TEE, we have
> > to map the OP-TEE area with PTE_EXT_XN to prevent the instruction
> > prefetcher from speculating into that area. With the current section
> > mapping we have to align OPTEE_SIZE to 1MiB boundaries. The second
> > problem comes with SRAM where the PBL might be running. This SRAM has
> > to be mapped executable, but at the same time we should map the
> > surrounding areas non executable which is not always possible with
> > 1MiB mapping granularity.
> > 
> > We now have everything in place to use two level page tables from PBL,
> > so use arch_remap_range() for the problematic cases.
> > 
> > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> > ---
> >  arch/arm/cpu/mmu_32.c | 31 +++++++------------------------
> >  1 file changed, 7 insertions(+), 24 deletions(-)
> > 
> > diff --git a/arch/arm/cpu/mmu_32.c b/arch/arm/cpu/mmu_32.c
> > index 785b20c7fd..705d27a045 100644
> > --- a/arch/arm/cpu/mmu_32.c
> > +++ b/arch/arm/cpu/mmu_32.c
> > @@ -111,8 +111,10 @@ void dma_flush_range(void *ptr, size_t size)
> >  	unsigned long end = start + size;
> >  
> >  	__dma_flush_range(start, end);
> > +#ifndef __PBL__
> >  	if (outer_cache.flush_range)
> >  		outer_cache.flush_range(start, end);
> > +#endif
> 
> Meh. I see why this is ok (L2X0 currently initialized in initcall), but this
> #ifdef looks a bit too fragile. Perhaps, we could do this in <asm/mmu.h> instead?
> 
> #ifdef __PBL__
> /* Existing platforms with non-architected outer cache initialize it
>  * outside PBL and new ones will likely only have architected caches,
>  * so we provide a dummy here
>  */
> static __maybe_unused struct outer_cache_fns outer_cache;
> #else
> extern struct outer_cache_fns outer_cache;
> #endif

Ok.

Sascha

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