[PATCH 17/21] MIPS: c-r4k: prettify code in __BUILD_BLAST_CACHE_RANGE

[Denis Orlov]

Even though the original code was taken from Linux, it is quite old and
crufty. Replace the 'while (1)' loop with the 'for' one, use const for
constant variables and use ALIGN_DOWN macro instead of repeating its
code.

Signed-off-by: Denis Orlov <denorl2009 at gmail.com>
---
 arch/mips/lib/c-r4k.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index 8bc0a7a411..6389ab9be2 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -27,19 +27,16 @@
 static inline void blast_##pfx##cache##_range(unsigned long start,	\
 					      unsigned long end)	\
 {									\
-	unsigned long lsize = current_cpu_data.desc.linesz;		\
-	unsigned long addr = start & ~(lsize - 1);			\
-	unsigned long aend = (end - 1) & ~(lsize - 1);			\
+	const unsigned long lsize = current_cpu_data.desc.linesz;	\
+	const unsigned long astart = ALIGN_DOWN(start, lsize);		\
+	const unsigned long aend = ALIGN_DOWN(end - 1, lsize);		\
+	unsigned long addr;						\
 									\
 	if (current_cpu_data.desc.flags & MIPS_CACHE_NOT_PRESENT)	\
 		return;							\
 									\
-	while (1) {							\
+	for (addr = astart; addr <= aend; addr += lsize)		\
 		cache_op(hitop, addr);					\
-		if (addr == aend)					\
-			break;						\
-		addr += lsize;						\
-	}								\
 }
 
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
-- 
2.41.0