[PATCH 19/21] MIPS: c-r4k: do flush secondary cache

[Denis Orlov]

Even though we probe for the secondary cache, we don't actually utilize
it when flushing. It seems that the reason for this is that no MIPS
board currently supported in barebox actually has secondary caches and
thus requires the additional logic in handling them.

Add the required functions and calls to them. This will make it easier
to add support for boards that do happen to have secondary caches.

Signed-off-by: Denis Orlov <denorl2009 at gmail.com>
---
 arch/mips/include/asm/cacheops.h |  5 +++++
 arch/mips/lib/c-r4k.c            | 12 ++++++------
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 9f60e0287d..1e4e361e22 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -12,6 +12,7 @@
  */
 #define Cache_I				0x00
 #define Cache_D				0x01
+#define Cache_SD			0x03
 
 #define Index_Writeback_Inv		0x00
 #define Index_Store_Tag			0x08
@@ -23,9 +24,13 @@
  */
 #define Index_Invalidate_I		(Cache_I | Index_Writeback_Inv)
 #define Index_Writeback_Inv_D		(Cache_D | Index_Writeback_Inv)
+#define Index_Writeback_Inv_SD		(Cache_SD | Index_Writeback_Inv)
 #define Index_Store_Tag_I		(Cache_I | Index_Store_Tag)
 #define Index_Store_Tag_D		(Cache_D | Index_Store_Tag)
+#define Index_Store_Tag_SD		(Cache_SD | Index_Store_Tag)
 #define Hit_Invalidate_D		(Cache_D | Hit_Invalidate)
+#define Hit_Invalidate_SD		(Cache_SD | Hit_Invalidate)
 #define Hit_Writeback_Inv_D		(Cache_D | Hit_Writeback_Inv)
+#define Hit_Writeback_Inv_SD		(Cache_SD | Hit_Writeback_Inv)
 
 #endif	/* __ASM_CACHEOPS_H */
diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index d3855bd756..2fb4e90138 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -60,30 +60,30 @@ static inline void blast_##pfx##cache##_range(unsigned long start,	\
 
 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D)
 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD)
 
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD)
 __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D)
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD)
 
 void flush_cache_all(void)
 {
 	blast_dcache();
 	blast_icache();
-
-	/* secondatory cache skipped */
+	blast_scache();
 }
 
 void dma_flush_range(unsigned long start, unsigned long end)
 {
 	blast_dcache_range(start, end);
-
-	/* secondatory cache skipped */
+	blast_scache_range(start, end);
 }
 
 void dma_inv_range(unsigned long start, unsigned long end)
 {
 	blast_inv_dcache_range(start, end);
-
-	/* secondatory cache skipped */
+	blast_inv_scache_range(start, end);
 }
 
 void r4k_cache_init(void);
-- 
2.41.0