[PATCH 1/5] ARM: remove samsung arch

Sascha Hauer s.hauer at pengutronix.de
Tue Feb 28 05:57:23 PST 2023


arch/arm/mach-samsung/ hasn't seen any active maintenance or interest
for a long time. Remove the architecture, boards and defconfig files

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 Documentation/boards/s3c/Digi-a9m2440.rst     |  93 --
 Documentation/boards/samsung.rst              |   8 -
 arch/arm/Kconfig                              |  19 -
 arch/arm/Makefile                             |  13 -
 arch/arm/boards/a9m2410/Makefile              |   4 -
 arch/arm/boards/a9m2410/a9m2410.c             | 136 ---
 arch/arm/boards/a9m2410/config.h              | 109 ---
 arch/arm/boards/a9m2410/env/bin/_update       |  36 -
 arch/arm/boards/a9m2410/env/bin/boot          |  38 -
 arch/arm/boards/a9m2410/env/bin/init          |  30 -
 arch/arm/boards/a9m2410/env/bin/update_kernel |  13 -
 arch/arm/boards/a9m2410/env/bin/update_root   |  11 -
 arch/arm/boards/a9m2410/env/config            |  26 -
 arch/arm/boards/a9m2410/lowlevel_init.S       |  39 -
 arch/arm/boards/a9m2440/Makefile              |   5 -
 arch/arm/boards/a9m2440/a9m2410dev.c          |  82 --
 arch/arm/boards/a9m2440/a9m2440.c             | 143 ----
 arch/arm/boards/a9m2440/baseboards.h          |   6 -
 arch/arm/boards/a9m2440/config.h              |  60 --
 arch/arm/boards/a9m2440/env/bin/_update       |  34 -
 arch/arm/boards/a9m2440/env/bin/boot          |  40 -
 arch/arm/boards/a9m2440/env/bin/init          |  30 -
 arch/arm/boards/a9m2440/env/bin/update_kernel |  13 -
 arch/arm/boards/a9m2440/env/bin/update_root   |  13 -
 arch/arm/boards/a9m2440/env/config            |  26 -
 arch/arm/boards/a9m2440/lowlevel_init.S       | 243 ------
 arch/arm/boards/friendlyarm-mini2440/Kconfig  |  35 -
 arch/arm/boards/friendlyarm-mini2440/Makefile |   5 -
 arch/arm/boards/friendlyarm-mini2440/config.h | 118 ---
 .../boards/friendlyarm-mini2440/env/boot/nand |   4 -
 .../friendlyarm-mini2440/env/config-board     |  16 -
 .../env/init/mtdparts-nand                    |   6 -
 .../friendlyarm-mini2440/lowlevel_init.S      |  44 -
 .../boards/friendlyarm-mini2440/mini2440.c    | 341 --------
 arch/arm/boards/friendlyarm-mini6410/Makefile |   5 -
 arch/arm/boards/friendlyarm-mini6410/config.h |  10 -
 .../defaultenv-friendlyarm-mini6410/config    |  52 --
 .../boards/friendlyarm-mini6410/lowlevel.c    |  13 -
 .../boards/friendlyarm-mini6410/mini6410.c    | 302 -------
 arch/arm/boards/friendlyarm-tiny210/Makefile  |   4 -
 arch/arm/boards/friendlyarm-tiny210/config.h  |  21 -
 .../arm/boards/friendlyarm-tiny210/lowlevel.c | 100 ---
 arch/arm/boards/friendlyarm-tiny210/tiny210.c | 102 ---
 arch/arm/boards/friendlyarm-tiny6410/Kconfig  |  21 -
 arch/arm/boards/friendlyarm-tiny6410/Makefile |   6 -
 arch/arm/boards/friendlyarm-tiny6410/config.h |  10 -
 .../defaultenv-friendlyarm-tiny6410/config    |  52 --
 .../friendlyarm-tiny6410/development-board.c  |  94 ---
 .../boards/friendlyarm-tiny6410/lowlevel.c    |  13 -
 .../boards/friendlyarm-tiny6410/tiny6410.c    |  72 --
 .../boards/friendlyarm-tiny6410/tiny6410.h    |   4 -
 arch/arm/configs/a9m2410_defconfig            |  32 -
 arch/arm/configs/a9m2440_defconfig            |  34 -
 .../configs/friendlyarm_mini2440_defconfig    |  41 -
 .../configs/friendlyarm_mini6410_defconfig    |  34 -
 .../arm/configs/friendlyarm_tiny210_defconfig |   7 -
 .../configs/friendlyarm_tiny6410_defconfig    |  35 -
 arch/arm/mach-samsung/Kconfig                 | 178 ----
 arch/arm/mach-samsung/Makefile                |  14 -
 arch/arm/mach-samsung/bbu-nand-s3c24x0.c      |  85 --
 arch/arm/mach-samsung/clocks-s3c24xx.c        | 145 ----
 arch/arm/mach-samsung/clocks-s3c64xx.c        | 338 --------
 arch/arm/mach-samsung/clocks-s5pcxx.c         |  98 ---
 arch/arm/mach-samsung/generic.c               |  51 --
 arch/arm/mach-samsung/gpio-s3c24x0.c          | 167 ----
 arch/arm/mach-samsung/gpio-s3c64xx.c          | 302 -------
 arch/arm/mach-samsung/gpio-s5pcxx.c           | 124 ---
 arch/arm/mach-samsung/include/mach/bbu.h      |  18 -
 .../include/mach/devices-s3c24xx.h            |  55 --
 .../include/mach/devices-s3c64xx.h            |  40 -
 .../mach-samsung/include/mach/iomux-s3c24x0.h | 422 ---------
 .../mach-samsung/include/mach/iomux-s3c64xx.h | 542 ------------
 .../mach-samsung/include/mach/iomux-s5pcxx.h  | 798 ------------------
 arch/arm/mach-samsung/include/mach/iomux.h    |  28 -
 .../mach-samsung/include/mach/s3c-busctl.h    |  32 -
 .../mach-samsung/include/mach/s3c-clocks.h    |  28 -
 .../mach-samsung/include/mach/s3c-generic.h   |  62 --
 .../arm/mach-samsung/include/mach/s3c-iomap.h |  23 -
 arch/arm/mach-samsung/include/mach/s3c-mci.h  |  39 -
 .../include/mach/s3c24xx-clocks.h             |  24 -
 .../mach-samsung/include/mach/s3c24xx-fb.h    |  55 --
 .../mach-samsung/include/mach/s3c24xx-gpio.h  |  77 --
 .../mach-samsung/include/mach/s3c24xx-iomap.h |  65 --
 .../mach-samsung/include/mach/s3c24xx-nand.h  |  57 --
 .../include/mach/s3c64xx-clocks.h             |  67 --
 .../mach-samsung/include/mach/s3c64xx-iomap.h |  51 --
 .../mach-samsung/include/mach/s5pcxx-clocks.h |  55 --
 .../mach-samsung/include/mach/s5pcxx-iomap.h  |  46 -
 arch/arm/mach-samsung/lowlevel-s3c24x0.S      | 305 -------
 arch/arm/mach-samsung/lowlevel-s5pcxx.c       |  61 --
 arch/arm/mach-samsung/mem-s3c24x0.c           |  79 --
 arch/arm/mach-samsung/mem-s3c64xx.c           |  66 --
 arch/arm/mach-samsung/mem-s5pcxx.c            | 320 -------
 arch/arm/mach-samsung/reset_source.c          |  56 --
 arch/arm/mach-samsung/s3c-timer.c             | 119 ---
 scripts/.gitignore                            |   1 -
 scripts/Kconfig                               |   7 -
 scripts/Makefile                              |   1 -
 98 files changed, 8004 deletions(-)
 delete mode 100644 Documentation/boards/s3c/Digi-a9m2440.rst
 delete mode 100644 Documentation/boards/samsung.rst
 delete mode 100644 arch/arm/boards/a9m2410/Makefile
 delete mode 100644 arch/arm/boards/a9m2410/a9m2410.c
 delete mode 100644 arch/arm/boards/a9m2410/config.h
 delete mode 100644 arch/arm/boards/a9m2410/env/bin/_update
 delete mode 100644 arch/arm/boards/a9m2410/env/bin/boot
 delete mode 100644 arch/arm/boards/a9m2410/env/bin/init
 delete mode 100644 arch/arm/boards/a9m2410/env/bin/update_kernel
 delete mode 100644 arch/arm/boards/a9m2410/env/bin/update_root
 delete mode 100644 arch/arm/boards/a9m2410/env/config
 delete mode 100644 arch/arm/boards/a9m2410/lowlevel_init.S
 delete mode 100644 arch/arm/boards/a9m2440/Makefile
 delete mode 100644 arch/arm/boards/a9m2440/a9m2410dev.c
 delete mode 100644 arch/arm/boards/a9m2440/a9m2440.c
 delete mode 100644 arch/arm/boards/a9m2440/baseboards.h
 delete mode 100644 arch/arm/boards/a9m2440/config.h
 delete mode 100644 arch/arm/boards/a9m2440/env/bin/_update
 delete mode 100644 arch/arm/boards/a9m2440/env/bin/boot
 delete mode 100644 arch/arm/boards/a9m2440/env/bin/init
 delete mode 100644 arch/arm/boards/a9m2440/env/bin/update_kernel
 delete mode 100644 arch/arm/boards/a9m2440/env/bin/update_root
 delete mode 100644 arch/arm/boards/a9m2440/env/config
 delete mode 100644 arch/arm/boards/a9m2440/lowlevel_init.S
 delete mode 100644 arch/arm/boards/friendlyarm-mini2440/Kconfig
 delete mode 100644 arch/arm/boards/friendlyarm-mini2440/Makefile
 delete mode 100644 arch/arm/boards/friendlyarm-mini2440/config.h
 delete mode 100644 arch/arm/boards/friendlyarm-mini2440/env/boot/nand
 delete mode 100644 arch/arm/boards/friendlyarm-mini2440/env/config-board
 delete mode 100644 arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand
 delete mode 100644 arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S
 delete mode 100644 arch/arm/boards/friendlyarm-mini2440/mini2440.c
 delete mode 100644 arch/arm/boards/friendlyarm-mini6410/Makefile
 delete mode 100644 arch/arm/boards/friendlyarm-mini6410/config.h
 delete mode 100644 arch/arm/boards/friendlyarm-mini6410/defaultenv-friendlyarm-mini6410/config
 delete mode 100644 arch/arm/boards/friendlyarm-mini6410/lowlevel.c
 delete mode 100644 arch/arm/boards/friendlyarm-mini6410/mini6410.c
 delete mode 100644 arch/arm/boards/friendlyarm-tiny210/Makefile
 delete mode 100644 arch/arm/boards/friendlyarm-tiny210/config.h
 delete mode 100644 arch/arm/boards/friendlyarm-tiny210/lowlevel.c
 delete mode 100644 arch/arm/boards/friendlyarm-tiny210/tiny210.c
 delete mode 100644 arch/arm/boards/friendlyarm-tiny6410/Kconfig
 delete mode 100644 arch/arm/boards/friendlyarm-tiny6410/Makefile
 delete mode 100644 arch/arm/boards/friendlyarm-tiny6410/config.h
 delete mode 100644 arch/arm/boards/friendlyarm-tiny6410/defaultenv-friendlyarm-tiny6410/config
 delete mode 100644 arch/arm/boards/friendlyarm-tiny6410/development-board.c
 delete mode 100644 arch/arm/boards/friendlyarm-tiny6410/lowlevel.c
 delete mode 100644 arch/arm/boards/friendlyarm-tiny6410/tiny6410.c
 delete mode 100644 arch/arm/boards/friendlyarm-tiny6410/tiny6410.h
 delete mode 100644 arch/arm/configs/a9m2410_defconfig
 delete mode 100644 arch/arm/configs/a9m2440_defconfig
 delete mode 100644 arch/arm/configs/friendlyarm_mini2440_defconfig
 delete mode 100644 arch/arm/configs/friendlyarm_mini6410_defconfig
 delete mode 100644 arch/arm/configs/friendlyarm_tiny210_defconfig
 delete mode 100644 arch/arm/configs/friendlyarm_tiny6410_defconfig
 delete mode 100644 arch/arm/mach-samsung/Kconfig
 delete mode 100644 arch/arm/mach-samsung/Makefile
 delete mode 100644 arch/arm/mach-samsung/bbu-nand-s3c24x0.c
 delete mode 100644 arch/arm/mach-samsung/clocks-s3c24xx.c
 delete mode 100644 arch/arm/mach-samsung/clocks-s3c64xx.c
 delete mode 100644 arch/arm/mach-samsung/clocks-s5pcxx.c
 delete mode 100644 arch/arm/mach-samsung/generic.c
 delete mode 100644 arch/arm/mach-samsung/gpio-s3c24x0.c
 delete mode 100644 arch/arm/mach-samsung/gpio-s3c64xx.c
 delete mode 100644 arch/arm/mach-samsung/gpio-s5pcxx.c
 delete mode 100644 arch/arm/mach-samsung/include/mach/bbu.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/devices-s3c64xx.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/iomux-s5pcxx.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/iomux.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c-busctl.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c-clocks.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c-generic.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c-iomap.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c-mci.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-clocks.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-iomap.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s5pcxx-clocks.h
 delete mode 100644 arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
 delete mode 100644 arch/arm/mach-samsung/lowlevel-s3c24x0.S
 delete mode 100644 arch/arm/mach-samsung/lowlevel-s5pcxx.c
 delete mode 100644 arch/arm/mach-samsung/mem-s3c24x0.c
 delete mode 100644 arch/arm/mach-samsung/mem-s3c64xx.c
 delete mode 100644 arch/arm/mach-samsung/mem-s5pcxx.c
 delete mode 100644 arch/arm/mach-samsung/reset_source.c
 delete mode 100644 arch/arm/mach-samsung/s3c-timer.c

diff --git a/Documentation/boards/s3c/Digi-a9m2440.rst b/Documentation/boards/s3c/Digi-a9m2440.rst
deleted file mode 100644
index 32d58b9a04..0000000000
--- a/Documentation/boards/s3c/Digi-a9m2440.rst
+++ /dev/null
@@ -1,93 +0,0 @@
-DIGI a9m2440
-============
-
-This CPU card is based on a Samsung S3C2440 CPU. The card is shipped with:
-
-  * S3C2440\@400 MHz or 533 MHz (ARM920T/ARMv4T)
-  * 16.9344 MHz crystal reference
-  * SDRAM 32/64/128 MiB
-
-     * Samsung K4M563233E-EE1H (one or two devices for 32 MiB or 64 MiB)
-
-       * 2M x 32bit x 4 Banks Mobile SDRAM
-       * CL2\@100 MHz (CAS/RAS delay 19ns)
-       * 105 MHz max
-       * column address size is 9 bits
-       *  Row cycle time: 69ns
-
-     * Samsung K4M513233C-DG75 (one or two devices for 64 MiB or 128 MiB)
-
-       * 4M x 32bit x 4 Banks Mobile SDRAM
-       * CL2\@100MHz (CAS/RAS delay 18ns)
-       * 111 MHz max
-       * column address size is 9 bits
-       * Row cycle time: 63ns
-
-     * 64ms refresh period (4k)
-     * 90 pin FBGA
-     * 32 bit data bits
-     * Extended temperature range (-25°C...85°C)
-
-  * NAND Flash 32/64/128 MiB
-
-     * Samsung KM29U512T (NAND01GW3A0AN6)
-
-       * 64 MiB 3,3V 8-bit
-       * ID: 0xEC, 0x76, 0x??, 0xBD
-
-     * Samsung KM29U256T
-
-       * 32 MiB 3,3V 8-bit
-       * ID: 0xEC, 0x75, 0x??, 0xBD
-
-     * ST Micro
-
-       * 128 MiB 3,3V 8-bit
-       * ID: 0x20, 0x79
-
-     * 30ns/40ns/20ns
-
-  * I2C interface, 100 KHz and 400 KHz
-
-     * Real Time Clock
-
-       * Dallas DS1337
-       * address 0x68
-
-     * EEPROM
-
-       * ST M24LC64
-       * address 0x50
-       * 16bit addressing
-
-  * LCD interface
-  * Touch Screen interface
-  * Camera interface
-  * I2S interface
-  * AC97 Audio-CODEC interface
-  * SD card interface
-  * 3 serial RS232 interfaces
-  * Host and device USB interface, USB1.1 compliant
-  * Ethernet interface
-
-    * 10Mbps, Cirrus Logic, CS8900A (on the CPU card)
-
-  * SPI interface
-  * JTAG interface
-
-How to get the binary image
----------------------------
-
-Configure with the default configuration:
-
-.. code-block:: sh
-
-  make ARCH=arm a9m2440_defconfig
-
-Build the binary image:
-
-.. code-block:: sh
-
-  make ARCH=arm CROSS_COMPILE=armv4compiler
-
-**NOTE:** replace the armv4compiler with your ARM v4 cross compiler.
diff --git a/Documentation/boards/samsung.rst b/Documentation/boards/samsung.rst
deleted file mode 100644
index f6f341301d..0000000000
--- a/Documentation/boards/samsung.rst
+++ /dev/null
@@ -1,8 +0,0 @@
-Samsung S3C/S5P
-===============
-
-.. toctree::
-  :glob:
-  :maxdepth: 1
-
-  s3c/*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8183f6d546..8681c81d2c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -177,24 +177,6 @@ config ARCH_SOCFPGA
 	select COMMON_CLK
 	select CLKDEV_LOOKUP
 
-config ARCH_S3C24xx
-	bool "Samsung S3C2410, S3C2440"
-	select ARCH_SAMSUNG
-	select CPU_ARM920T
-	select GENERIC_GPIO
-
-config ARCH_S5PCxx
-	bool "Samsung S5PC110, S5PV210"
-	select ARCH_SAMSUNG
-	select CPU_V7
-	select GENERIC_GPIO
-
-config ARCH_S3C64xx
-	bool "Samsung S3C64xx"
-	select ARCH_SAMSUNG
-	select CPU_V6
-	select GENERIC_GPIO
-
 config ARCH_STM32MP
 	bool "STMicroelectronics STM32MP"
 	select ARCH_STM32
@@ -311,7 +293,6 @@ source "arch/arm/mach-nomadik/Kconfig"
 source "arch/arm/mach-omap/Kconfig"
 source "arch/arm/mach-pxa/Kconfig"
 source "arch/arm/mach-rockchip/Kconfig"
-source "arch/arm/mach-samsung/Kconfig"
 source "arch/arm/mach-socfpga/Kconfig"
 source "arch/arm/mach-stm32mp/Kconfig"
 source "arch/arm/mach-versatile/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 124a3fc40c..55b3195310 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -119,14 +119,8 @@ machine-$(CONFIG_ARCH_ZYNQMP)		:= zynqmp
 # These are here only because they have a board specific config.h.
 # TODO: Get rid of board specific config.h and move these to
 # arch/arm/boards/Makefile aswell.
-board-$(CONFIG_MACH_A9M2410)			+= a9m2410
-board-$(CONFIG_MACH_A9M2440)			+= a9m2440
 board-$(CONFIG_MACH_AT91RM9200EK)		+= at91rm9200ek
-board-$(CONFIG_MACH_MINI2440)			+= friendlyarm-mini2440
-board-$(CONFIG_MACH_MINI6410)			+= friendlyarm-mini6410
 board-$(CONFIG_MACH_PCM027)			+= phytec-phycore-pxa270
-board-$(CONFIG_MACH_TINY210)			+= friendlyarm-tiny210
-board-$(CONFIG_MACH_TINY6410)			+= friendlyarm-tiny6410
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
@@ -158,13 +152,6 @@ endif
 
 KBUILD_BINARY := barebox.bin
 
-barebox.s5p: $(KBUILD_BINARY)
-	$(Q)scripts/s5p_cksum $< barebox.s5p
-
-ifeq ($(CONFIG_ARCH_S5PCxx),y)
-KBUILD_IMAGE := barebox.s5p
-endif
-
 quiet_cmd_mlo ?= IFT     $@
 	cmd_mlo ?= scripts/omap_signGP -o MLO -l $(TEXT_BASE) -c $<
 
diff --git a/arch/arm/boards/a9m2410/Makefile b/arch/arm/boards/a9m2410/Makefile
deleted file mode 100644
index 6c53eafae2..0000000000
--- a/arch/arm/boards/a9m2410/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-lwl-y += lowlevel_init.o
-obj-y += a9m2410.o
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
deleted file mode 100644
index 25022abde2..0000000000
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ /dev/null
@@ -1,136 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <asm/sections.h>
-#include <nand.h>
-#include <io.h>
-#include <mach/devices-s3c24xx.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c24xx-nand.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
-static struct s3c24x0_nand_platform_data nand_info = {
-	.nand_timing = CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1)
-};
-
-static int a9m2410_mem_init(void)
-{
-	resource_size_t size;
-
-	/*
-	 * Note: On this card the second SDRAM page is not used
-	 */
-	s3c24xx_disable_second_sdram_bank();
-	size = s3c24xx_get_memory_size();
-
-	/* ---------- configure the GPIOs ------------- */
-	writel(0x007FFFFF, S3C_GPACON);
-	writel(0x00000000, S3C_GPCCON);
-	writel(0x00000000, S3C_GPCUP);
-	writel(0x00000000, S3C_GPDCON);
-	writel(0x00000000, S3C_GPDUP);
-	writel(0xAAAAAAAA, S3C_GPECON);
-	writel(0x0000E03F, S3C_GPEUP);
-	writel(0x00000000, S3C_GPBCON);	/* all inputs */
-	writel(0x00000007, S3C_GPBUP);	/* pullup disabled for GPB0..3 */
-	writel(0x00009000, S3C_GPFCON);	/* GPF7 CLK_INT#, GPF6 Debug-LED */
-	writel(0x000000FF, S3C_GPFUP);
-	writel(readl(S3C_GPGDAT) | 0x0010, S3C_GPGDAT);	/* switch off LCD backlight */
-	writel(0xFF00A938, S3C_GPGCON);	/* switch off USB device */
-	writel(0x0000F000, S3C_GPGUP);
-	writel(readl(S3C_GPHDAT) | 0x100, S3C_GPHDAT);	/* switch BOOTINT/GPIO_ON# to high */
-	writel(0x000007FF, S3C_GPHUP);
-	writel(0x0029FAAA, S3C_GPHCON);
-	/*
-	 * USB port1 normal, USB port0 normal, USB1 pads for device
-	 * PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
-	 * 2nd SDRAM bank off (only bank 1 is used)
-	 */
-	writel(0x40140, S3C_MISCCR);
-
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, size);
-
-	return 0;
-}
-mem_initcall(a9m2410_mem_init);
-
-static const struct devfs_partition a9m2410_nand0_partitions[] = {
-	{
-		.offset = 0,
-		.size = 0x40000,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "self_raw",
-		.bbname = "self0",
-	}, {
-		.offset = DEVFS_PARTITION_APPEND,
-		.size = 0x20000,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "env_raw",
-		.bbname = "env0",
-	}, {
-		/* sentinel */
-	}
-};
-
-static int a9m2410_devices_init(void)
-{
-	uint32_t reg;
-
-	/* ----------- configure the access to the outer space ---------- */
-	reg = readl(S3C_BWSCON);
-
-	/* CS#1 to access the network controller */
-	reg &= ~0xf0;
-	reg |= 0xe0;
-	writel(0x1350, S3C_BANKCON1);
-
-	/* CS#2 to the dual 16550 UART */
-	reg &= ~0xf00;
-	reg |= 0x400;
-	writel(0x0d50, S3C_BANKCON2);
-
-	writel(reg, S3C_BWSCON);
-
-	/* release the reset signal to the network and UART device */
-	reg = readl(S3C_MISCCR);
-	reg |= 0x10000;
-	writel(reg, S3C_MISCCR);
-
-	/* ----------- the devices the boot loader should work with -------- */
-	s3c24xx_add_nand(&nand_info);
-	/*
-	 * SMSC 91C111 network controller on the baseboard
-	 * connected to CS line 1 and interrupt line
-	 * GPIO3, data width is 32 bit
-	 */
-	add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, S3C_CS1_BASE + 0x300,
-			16, IORESOURCE_MEM, NULL);
-
-	if (IS_ENABLED(CONFIG_NAND))
-		devfs_create_partitions("nand0", a9m2410_nand0_partitions);
-
-	armlinux_set_architecture(MACH_TYPE_A9M2410);
-
-	return 0;
-}
-
-device_initcall(a9m2410_devices_init);
-
-static int a9m2410_console_init(void)
-{
-	barebox_set_model("Digi A9M2410");
-	barebox_set_hostname("a9m2410");
-
-	s3c24xx_add_uart1();
-	return 0;
-}
-
-console_initcall(a9m2410_console_init);
diff --git a/arch/arm/boards/a9m2410/config.h b/arch/arm/boards/a9m2410/config.h
deleted file mode 100644
index dbe4bb32cb..0000000000
--- a/arch/arm/boards/a9m2410/config.h
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/**
- * @file
- * @brief Global defintions for the ARM S3C2410 based a9m2410 CPU card
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/**
- * The external clock reference is a 12.0MHz crystal
- */
-#define S3C24XX_CLOCK_REFERENCE 12000000
-
-/**
- * Define the main clock configuration to be used in register CLKDIVN
- *
- * We must limit the frequency of the connected SDRAMs with the clock ratio
- * setup to 1:2:4. This will result into FCLK:HCLK:PCLK = 200Mhz:100MHz:50MHz
- */
-#define BOARD_SPECIFIC_CLKDIVN 0x003
-
-/**
- * Define the MPLL configuration to be used in register MPLLCON
- *
- * We want the MPLL to run at 202.80MHz
- */
-#define BOARD_SPECIFIC_MPLL ((0xA1 << 12) + (3 << 4) + 1)
-
-/**
- * Define the UPLL configuration to be used in register UPLLCON
- *
- * We want the UPLL to run at 48.0MHz
- */
-#define BOARD_SPECIFIC_UPLL ((0x78 << 12) + (2 << 4) + 3)
-
-/*
- * SDRAM configuration for Samsung K4M563233E
- *  - 2M x 32Bit x 4 Banks Mobile SDRAM
- *  - 90 pin FBGA
- *  - CL2 at 100MHz
- */
-/*
- * SDRAM uses 32bit width
- */
-#define BOARD_SPECIFIC_BWSCON ((0x02 << 24) + (0x02 << 28))
-/*
- * 32MiB SDRAM in bank6
- *  - MT = 11 (= sync dram type)
- *  - Trcd = 00 (= CL2)
- *  - SCAN = 01 (= 9 bit columns)
- */
-#define BOARD_SPECIFIC_BANKCON6 ((0x3 << 15) + (0x0 << 2) + 0x1)
-/*
- * No memory in bank7
- */
-#define BOARD_SPECIFIC_BANKCON7 ((0x3 << 15) + (0x0 << 2) + 0x1)
-/*
- * SDRAM refresh settings
- *  - REFEN = 1 (= refresh enabled)
- *  - TREFMD = 0 (= auto refresh)
- *  - Trp = 00 (= 2 RAS precharge clocks)
- *  - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
- *  - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489
- */
-#define BOARD_SPECIFIC_REFRESH ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489)
-/*
- * SDRAM banksize
- *  - BURST_EN = 1 (= burst mode enabled)
- *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
- *  - SCLK_EN = 1 (= clock active only during accesses)
- *  - BK67MAP = 000 (= 32MiB)
- */
-#define BOARD_SPECIFIC_BANKSIZE ((1 << 7) + (1 << 5) + (0 << 4) + 0)
-/*
- * SDRAM mode register bank6
- * CL = 010 (= 2 clocks)
- */
-#define BOARD_SPECIFIC_MRSRB6 (0x2 << 4)
-/*
- * SDRAM mode register bank7
- * CL = 010 (= 2 clocks)
- */
-#define BOARD_SPECIFIC_MRSRB7 (0x2 << 4)
-
-/*
- * Flash access timings
- * Tacls  = 0ns (but 20ns data setup time)
- * Twrph0 = 25ns (write) 35ns (read)
- * Twrph1 = 10ns (10ns data hold time)
- * Read cycle time = 50ns
- *
- * Assumed HCLK is 100MHz
- * Tacls = 1 (-> 20ns)
- * Twrph0 = 3 (-> 40ns)
- * Twrph1 = 1 (-> 20ns)
- * Cycle time = 80ns
- */
-#define A9M2410_TACLS 1
-#define A9M2410_TWRPH0 3
-#define A9M2410_TWRPH1 1
-
-/* needed in the generic NAND boot code only */
-#ifdef CONFIG_S3C_NAND_BOOT
-# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1)
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/a9m2410/env/bin/_update b/arch/arm/boards/a9m2410/env/bin/_update
deleted file mode 100644
index 014bce3512..0000000000
--- a/arch/arm/boards/a9m2410/env/bin/_update
+++ /dev/null
@@ -1,36 +0,0 @@
-#!/bin/sh
-
-if [ -z "$part" -o -z "$image" ]; then
-	echo "define \$part and \$image"
-	exit 1
-fi
-
-if [ ! -e "$part" ]; then
-	echo "Partition $part does not exist"
-	exit 1
-fi
-
-if [ $# = 1 ]; then
-	image=$1
-fi
-
-if [ x$ip = xdhcp ]; then
-	dhcp
-fi
-
-ping $eth0.serverip
-if [ $? -ne 0 ] ; then
-	echo "update aborted"
-	exit 1
-fi
-
-unprotect $part
-
-echo
-echo "erasing partition $part"
-erase $part
-
-echo
-echo "flashing $image to $part"
-echo
-tftp $image $part
diff --git a/arch/arm/boards/a9m2410/env/bin/boot b/arch/arm/boards/a9m2410/env/bin/boot
deleted file mode 100644
index 59fa60e4e9..0000000000
--- a/arch/arm/boards/a9m2410/env/bin/boot
+++ /dev/null
@@ -1,38 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-if [ x$1 = xnand ]; then
-	root=nand
-	kernel=nand
-fi
-
-if [ x$1 = xnet ]; then
-	root=net
-	kernel=net
-fi
-
-if [ x$ip = xdhcp ]; then
-	bootargs="$bootargs ip=dhcp"
-else
-	bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
-fi
-
-if [ x$root = xnand ]; then
-	bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
-else
-	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
-fi
-
-bootargs="$bootargs mtdparts=\"NAND 32MiB 3,3V 8-bit:$nand_parts\""
-
-if [ x$kernel = xnet ]; then
-	if [ x$ip = xdhcp ]; then
-		dhcp
-	fi
-	tftp $uimage uImage || exit 1
-	bootm uImage
-else
-	bootm /dev/nand0.kernel.bb
-fi
-
diff --git a/arch/arm/boards/a9m2410/env/bin/init b/arch/arm/boards/a9m2410/env/bin/init
deleted file mode 100644
index dd94ef6be0..0000000000
--- a/arch/arm/boards/a9m2410/env/bin/init
+++ /dev/null
@@ -1,30 +0,0 @@
-#!/bin/sh
-
-PATH=/env/bin
-export PATH
-
-. /env/config
-
-if [ -e /dev/nand0 ]; then
-	addpart /dev/nand0 $nand_parts
-fi
-
-if [ -z $eth0.ethaddr ]; then
-	while [ -z $eth0.ethaddr ]; do
-		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
-	done
-	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
-fi
-
-echo
-echo -n "Hit any key to stop autoboot: "
-timeout -a $autoboot_timeout
-if [ $? != 0 ]; then
-	echo
-	echo "type update_kernel [<imagename>] to update kernel into flash"
-	echo "type update_root [<imagename>] to update rootfs into flash"
-	echo
-	exit
-fi
-
-boot
diff --git a/arch/arm/boards/a9m2410/env/bin/update_kernel b/arch/arm/boards/a9m2410/env/bin/update_kernel
deleted file mode 100644
index c43a55785b..0000000000
--- a/arch/arm/boards/a9m2410/env/bin/update_kernel
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-part=/dev/nand0.kernel.bb
-
-if [ x$1 = x ]; then
-	image=$uimage
-else
-	image=$1
-fi
-
-. /env/bin/_update $image
diff --git a/arch/arm/boards/a9m2410/env/bin/update_root b/arch/arm/boards/a9m2410/env/bin/update_root
deleted file mode 100644
index 34139e5dce..0000000000
--- a/arch/arm/boards/a9m2410/env/bin/update_root
+++ /dev/null
@@ -1,11 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-if [ x$1 = x ]; then
-	image=$jffs2
-else
-	image=$1
-fi
-
-. /env/bin/_update $image
diff --git a/arch/arm/boards/a9m2410/env/config b/arch/arm/boards/a9m2410/env/config
deleted file mode 100644
index 2b09318934..0000000000
--- a/arch/arm/boards/a9m2410/env/config
+++ /dev/null
@@ -1,26 +0,0 @@
-#!/bin/sh
-
-# can be either 'net' or 'nand''
-kernel=net
-root=net
-
-uimage=uImage-a9m2410
-jffs2=root-a9m2410.jffs2
-
-autoboot_timeout=3
-
-nfsroot="/nfsexport/OSELAS.BSP-Hesch-TMU-1/platform-FS_A9M2410/root"
-bootargs="console=ttySAC0,38400"
-
-nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
-rootpart_nand="/dev/mtdblock3"
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-#ip=dhcp
-
-# or set your networking parameters here
-eth0.ipaddr=192.168.42.31
-eth0.netmask=255.255.0.0
-eth0.gateway=192.168.23.1
-eth0.serverip=192.168.23.2
-#eth0.ethaddr=
diff --git a/arch/arm/boards/a9m2410/lowlevel_init.S b/arch/arm/boards/a9m2410/lowlevel_init.S
deleted file mode 100644
index 4c949b1efa..0000000000
--- a/arch/arm/boards/a9m2410/lowlevel_init.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <config.h>
-#include <linux/sizes.h>
-#include <mach/s3c-iomap.h>
-#include <asm/barebox-arm-head.h>
-
-	.section ".text_bare_init.barebox_arm_reset_vector","ax"
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
-
-	bl arm_cpu_lowlevel_init
-
-	bl s3c24x0_disable_wd
-
-	/* skip everything here if we are already running from SDRAM */
-	cmp pc, #S3C_SDRAM_BASE
-	blo 1f
-	cmp pc, #S3C_SDRAM_END
-	bhs 1f
-
-	b out
-
-/* we are running from NOR or NAND/SRAM memory. Do further initialisation */
-1:
-	bl s3c24x0_pll_init
-
-	bl s3c24x0_sdram_init
-
-#ifdef CONFIG_S3C_NAND_BOOT
-/* up to here we are running from the internal SRAM area */
-	bl s3c24x0_nand_boot
-#endif
-out:
-	mov r0, #S3C_SDRAM_BASE
-	mov r1, #SZ_32M
-	mov r2, #0
-	b barebox_arm_entry
diff --git a/arch/arm/boards/a9m2440/Makefile b/arch/arm/boards/a9m2440/Makefile
deleted file mode 100644
index e32c0aca64..0000000000
--- a/arch/arm/boards/a9m2440/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-lwl-y += lowlevel_init.o
-obj-y += a9m2440.o
-obj-$(CONFIG_MACH_A9M2410DEV) += a9m2410dev.o
diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c
deleted file mode 100644
index 627a8c6158..0000000000
--- a/arch/arm/boards/a9m2440/a9m2410dev.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2009 Juergen Beisert
-
-/**
- * @file
- * @brief a9m2410dev Baseboad specific initialization routines
- *
- */
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-#include "baseboards.h"
-
-/**
- * Initialize the CPU to be able to work with the a9m2410dev evaluation board
- */
-int a9m2410dev_devices_init(void)
-{
-	unsigned int reg;
-
-	/* ---------- configure the GPIOs ------------- */
-	writel(0x007FFFFF, S3C_GPACON);
-	writel(0x00000000, S3C_GPCCON);
-	writel(0x00000000, S3C_GPCUP);
-	writel(0x00000000, S3C_GPDCON);
-	writel(0x00000000, S3C_GPDUP);
-	writel(0xAAAAAAAA, S3C_GPECON);
-	writel(0x0000E03F, S3C_GPEUP);
-	writel(0x00000000, S3C_GPBCON);	/* all inputs */
-	writel(0x00000007, S3C_GPBUP);	/* pullup disabled for GPB0..3 */
-	writel(0x00009000, S3C_GPFCON);	/* GPF7 CLK_INT#, GPF6 Debug-LED */
-	writel(0x000000FF, S3C_GPFUP);
-	writel(readl(S3C_GPGDAT) | 0x1010, S3C_GPGDAT);	/* switch off IDLE_SW#, switch off LCD backlight */
-	writel(0x0100A93A, S3C_GPGCON);	/* switch on USB device */
-	writel(0x0000F000, S3C_GPGUP);
-	writel(0x0029FAAA, S3C_GPHCON);
-
-	writel((1 << 12) | (0 << 11), S3C_GPJDAT);
-	writel(0x0016aaaa, S3C_GPJCON);
-	writel(~((0<<12)| (1<<11)), S3C_GPJUP);
-
-	writel((0 << 12) | (0 << 11), S3C_GPJDAT);
-	writel(0x0016aaaa, S3C_GPJCON);
-	writel(0x00001fff, S3C_GPJUP);
-
-	writel(0x00000000, S3C_DSC0);
-	writel(0x00000000, S3C_DSC1);
-
-	/*
-	 * USB port1 normal, USB port0 normal, USB1 pads for device
-	 * PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
-	 */
-	writel((readl(S3C_MISCCR) & ~0xFFFF) | 0x0140, S3C_MISCCR);
-
-	/* ----------- configure the access to the outer space ---------- */
-	reg = readl(S3C_BWSCON);
-
-	/* CS#1 to access the network controller */
-	reg &= ~0xf0;
-	reg |= 0xe0;
-	writel(0x1350, S3C_BANKCON1);
-
-	/* CS#2 to the dual 16550 UART */
-	reg &= ~0xf00;
-	reg |= 0x400;
-	writel(0x0d50, S3C_BANKCON2);
-
-	writel(reg, S3C_BWSCON);
-
-	/* release the reset signal to the network and UART device */
-	reg = readl(S3C_MISCCR);
-	reg |= 0x10000;
-	writel(reg, S3C_MISCCR);
-
-	return 0;
-}
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
deleted file mode 100644
index 9a3eaef294..0000000000
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ /dev/null
@@ -1,143 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <asm/armlinux.h>
-#include <asm/sections.h>
-#include <generated/mach-types.h>
-#include <nand.h>
-#include <io.h>
-#include <mach/devices-s3c24xx.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c24xx-nand.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-#include "baseboards.h"
-
-static struct s3c24x0_nand_platform_data nand_info = {
-	.nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
-};
-
-static int a9m2440_check_for_ram(uint32_t addr)
-{
-	uint32_t tmp1, tmp2;
-	int rc = 0;
-
-	tmp1 = readl(addr);
-	tmp2 = readl(addr + sizeof(uint32_t));
-
-	writel(0xaaaaaaaa, addr);
-	writel(0x55555555, addr + sizeof(uint32_t));
-	if ((readl(addr) != 0xaaaaaaaa) || (readl(addr + sizeof(uint32_t)) != 0x55555555))
-		rc = 1;	/* seems no RAM */
-
-	writel(0x55555555, addr);
-	writel(0xaaaaaaaa, addr + sizeof(uint32_t));
-	if ((readl(addr) != 0x55555555) || (readl(addr + sizeof(uint32_t)) != 0xaaaaaaaa))
-		rc = 1;	/* seems no RAM */
-
-	writel(tmp1, addr);
-	writel(tmp2, addr + sizeof(uint32_t));
-
-	return rc;
-}
-
-static int a9m2440_mem_init(void)
-{
-	/*
-	 * The special SDRAM setup code for this machine will always enable
-	 * both SDRAM banks. But the second SDRAM device may not exists!
-	 * So we must check here, if the second bank is populated to get the
-	 * correct RAM size.
-	 */
-	switch (readl(S3C_BANKSIZE) & 0x7) {
-	case 0:
-		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 32 * 1024 * 1024))
-			s3c24xx_disable_second_sdram_bank();
-		break;
-	case 1:
-		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 64 * 1024 * 1024))
-			s3c24xx_disable_second_sdram_bank();
-		break;
-	case 2:
-		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 128 * 1024 * 1024))
-			s3c24xx_disable_second_sdram_bank();
-		break;
-	case 4:
-	case 5:
-	case 6:		/* not supported on this machine */
-		break;
-	default:
-		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 16 * 1024 * 1024))
-			s3c24xx_disable_second_sdram_bank();
-		break;
-	}
-
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size());
-
-	return 0;
-}
-mem_initcall(a9m2440_mem_init);
-
-static int a9m2440_devices_init(void)
-{
-	uint32_t reg;
-
-	/* ----------- configure the access to the outer space ---------- */
-	reg = readl(S3C_BWSCON);
-
-	/* CS#5 to access the network controller */
-	reg &= ~0x00f00000;
-	reg |=  0x00d00000;	/* 16 bit */
-	writel(0x1f4c, S3C_BANKCON5);
-
-	writel(reg, S3C_BWSCON);
-
-#ifdef CONFIG_MACH_A9M2410DEV
-	a9m2410dev_devices_init();
-#endif
-
-	/* release the reset signal to external devices */
-	reg = readl(S3C_MISCCR);
-	reg |= 0x10000;
-	writel(reg, S3C_MISCCR);
-
-	/* ----------- the devices the boot loader should work with -------- */
-	s3c24xx_add_nand(&nand_info);
-	/*
-	 * cs8900 network controller onboard
-	 * Connected to CS line 5 + A24 and interrupt line EINT9,
-	 * data width is 16 bit
-	 */
-	add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL,
-			S3C_CS5_BASE + (1 << 24) + 0x300, 16, IORESOURCE_MEM, NULL);
-
-#ifdef CONFIG_NAND
-	/* ----------- add some vital partitions -------- */
-	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
-	dev_add_bb_dev("self_raw", "self0");
-
-	devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
-	dev_add_bb_dev("env_raw", "env0");
-#endif
-	armlinux_set_architecture(MACH_TYPE_A9M2440);
-
-	return 0;
-}
-
-device_initcall(a9m2440_devices_init);
-
-static int a9m2440_console_init(void)
-{
-	barebox_set_model("Digi A9M2440");
-	barebox_set_hostname("a9m2440");
-
-	s3c24xx_add_uart1();
-	return 0;
-}
-
-console_initcall(a9m2440_console_init);
diff --git a/arch/arm/boards/a9m2440/baseboards.h b/arch/arm/boards/a9m2440/baseboards.h
deleted file mode 100644
index be4ae65e82..0000000000
--- a/arch/arm/boards/a9m2440/baseboards.h
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2009 Juergen Beisert
-
-#ifdef CONFIG_MACH_A9M2410DEV
-extern int a9m2410dev_devices_init(void);
-#endif
diff --git a/arch/arm/boards/a9m2440/config.h b/arch/arm/boards/a9m2440/config.h
deleted file mode 100644
index c22ff53036..0000000000
--- a/arch/arm/boards/a9m2440/config.h
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/**
- * @file
- * @brief Global defintions for the ARM S3C2440 based a9m2440 CPU card
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/**
- * The external clock reference is a 16.9344 MHz crystal
- */
-#define S3C24XX_CLOCK_REFERENCE 16934400
-
-/**
- * Define the main clock configuration to be used in register CLKDIVN
- *
- * We must limit the frequency of the connected SDRAMs with the clock ratio
- * setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 400Mhz:100MHz:50MHz
- */
-#define BOARD_SPECIFIC_CLKDIVN 0x05
-
-/**
- * Define the MPLL configuration to be used in register MPLLCON
- *
- * We want the MPLL to run at 399.65 MHz
- */
-#define BOARD_SPECIFIC_MPLL ((0x6e << 12) + (3 << 4) + 1)
-
-/**
- * Define the UPLL configuration to be used in register UPLLCON
- *
- * We want the UPLL to run at 47.98 MHz
- */
-#define BOARD_SPECIFIC_UPLL ((0x3c << 12) + (4 << 4) + 2)
-
-/*
- * Flash access timings
- * Tacls  = 0ns (but 20ns data setup time)
- * Twrph0 = 25ns (write) 35ns (read)
- * Twrph1 = 10ns (10ns data hold time)
- * Read cycle time = 50ns
- *
- * Assumed HCLK is 100MHz
- * Tacls = 1 (-> 20ns)
- * Twrph0 = 3 (-> 40ns)
- * Twrph1 = 1 (-> 20ns)
- * Cycle time = 80ns
- */
-#define A9M2440_TACLS 1
-#define A9M2440_TWRPH0 3
-#define A9M2440_TWRPH1 1
-
-/* needed in the generic NAND boot code only */
-#ifdef CONFIG_S3C_NAND_BOOT
-# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/a9m2440/env/bin/_update b/arch/arm/boards/a9m2440/env/bin/_update
deleted file mode 100644
index b10682ece4..0000000000
--- a/arch/arm/boards/a9m2440/env/bin/_update
+++ /dev/null
@@ -1,34 +0,0 @@
-#!/bin/sh
-
-if [ -z "$part" -o -z "$image" ]; then
-	echo "define \$part and \$image"
-	exit 1
-fi
-
-if [ ! -e "$part" ]; then
-	echo "Partition $part does not exist"
-	exit 1
-fi
-
-if [ $# = 1 ]; then
-	image=$1
-fi
-
-if [ x$ip = xdhcp ]; then
-	dhcp
-fi
-
-ping $eth0.serverip
-if [ $? -ne 0 ] ; then
-	echo "update aborted"
-	exit 1
-fi
-
-echo
-echo "erasing partition $part"
-erase $part
-
-echo
-echo "flashing $image to $part"
-echo
-tftp $image $part
diff --git a/arch/arm/boards/a9m2440/env/bin/boot b/arch/arm/boards/a9m2440/env/bin/boot
deleted file mode 100644
index 86e22cf9ff..0000000000
--- a/arch/arm/boards/a9m2440/env/bin/boot
+++ /dev/null
@@ -1,40 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-if [ x$1 = xnand ]; then
-	root=nand
-	kernel=nand
-fi
-
-if [ x$1 = xnet ]; then
-	root=net
-	kernel=net
-fi
-
-if [ x$root = xnand ]; then
-	bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
-fi
-if [ x$root = xnet ]; then
-	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
-	if [ x$ip = xdhcp ]; then
-		bootargs="$bootargs ip=dhcp"
-	else
-		bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
-	fi
-fi
-
-bootargs="$bootargs mtdparts=\"NAND 32MiB 3,3V 8-bit:$nand_parts\""
-
-bootargs="$bootargs cs89x0_media=rj45 cs89x0_mac=$eth0.ethaddr"
-
-if [ x$kernel = xnet ]; then
-	if [ x$ip = xdhcp ]; then
-		dhcp
-	fi
-	tftp $uimage uImage || exit 1
-	bootm uImage
-else
-	bootm /dev/nand0.kernel.bb
-fi
-
diff --git a/arch/arm/boards/a9m2440/env/bin/init b/arch/arm/boards/a9m2440/env/bin/init
deleted file mode 100644
index dd94ef6be0..0000000000
--- a/arch/arm/boards/a9m2440/env/bin/init
+++ /dev/null
@@ -1,30 +0,0 @@
-#!/bin/sh
-
-PATH=/env/bin
-export PATH
-
-. /env/config
-
-if [ -e /dev/nand0 ]; then
-	addpart /dev/nand0 $nand_parts
-fi
-
-if [ -z $eth0.ethaddr ]; then
-	while [ -z $eth0.ethaddr ]; do
-		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
-	done
-	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
-fi
-
-echo
-echo -n "Hit any key to stop autoboot: "
-timeout -a $autoboot_timeout
-if [ $? != 0 ]; then
-	echo
-	echo "type update_kernel [<imagename>] to update kernel into flash"
-	echo "type update_root [<imagename>] to update rootfs into flash"
-	echo
-	exit
-fi
-
-boot
diff --git a/arch/arm/boards/a9m2440/env/bin/update_kernel b/arch/arm/boards/a9m2440/env/bin/update_kernel
deleted file mode 100644
index c43a55785b..0000000000
--- a/arch/arm/boards/a9m2440/env/bin/update_kernel
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-part=/dev/nand0.kernel.bb
-
-if [ x$1 = x ]; then
-	image=$uimage
-else
-	image=$1
-fi
-
-. /env/bin/_update $image
diff --git a/arch/arm/boards/a9m2440/env/bin/update_root b/arch/arm/boards/a9m2440/env/bin/update_root
deleted file mode 100644
index 46cbca5beb..0000000000
--- a/arch/arm/boards/a9m2440/env/bin/update_root
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-part=/dev/nand0.root.bb
-
-if [ x$1 = x ]; then
-	image=$jffs2
-else
-	image=$1
-fi
-
-. /env/bin/_update $image
diff --git a/arch/arm/boards/a9m2440/env/config b/arch/arm/boards/a9m2440/env/config
deleted file mode 100644
index d1fb01b731..0000000000
--- a/arch/arm/boards/a9m2440/env/config
+++ /dev/null
@@ -1,26 +0,0 @@
-#!/bin/sh
-
-# can be either 'net' or 'nand''
-kernel=net
-root=net
-
-uimage=uImage-a9m2440
-jffs2=root-a9m2440.jffs2
-
-autoboot_timeout=3
-
-nfsroot="/nfsexport/OSELAS.BSP-Hesch-TMU-1/platform-FS_A9M2440/root"
-bootargs="console=ttySAC0,38400"
-
-nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
-rootpart_nand="/dev/mtdblock3"
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-#ip=dhcp
-
-# or set your networking parameters here
-eth0.ipaddr=192.168.42.32
-eth0.netmask=255.255.0.0
-eth0.gateway=192.168.23.1
-eth0.serverip=192.168.23.2
-#eth0.ethaddr=
diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S
deleted file mode 100644
index 585863f9d4..0000000000
--- a/arch/arm/boards/a9m2440/lowlevel_init.S
+++ /dev/null
@@ -1,243 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <config.h>
-#include <linux/sizes.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c24xx-gpio.h>
-#include <asm/barebox-arm-head.h>
-
-	.section ".text_bare_init.barebox_arm_reset_vector","ax"
-
-/*
- * To be able to setup the SDRAM interface correctly, we need some
- * external information about the connected SDRAM devices.
- *
- * When we set GPH8, we can read at GPB:
- * Bit 0..1: Memory device size -> 00=16M, 01=64M, 10=32M, 11=128M
- * Bit 2: CL setting
- *
- * Some remarks: The CL setting seems useless. It always signals a CL3
- * requirement, but the SDRAM types I found on the cards are supporting
- * CL2 @ 100 MHz. But also these SDRAM types are only support 105 MHz max.
- * So, we never need CL3 because we can't run the CPU at 533 MHz (which
- * implies an 133 MHz SDRAM clock).
- * All devices are connected via 32 bit databus
- *
- * Note: I was able to check the 32 MiB and 64 MiB configuration only. I didn't
- * had access to a 16 MiB nor 128 MiB config.
- *
- */
-
-sdram_init:
-	/*
-	 * Read the configuration. After reset until any GPIO port is
-	 * configured yet, these pins show external settings, to detect
-	 * the SDRAM size.
-	 */
-	ldr r1, =S3C_GPBDAT
-	ldr r4, [r1]
-	and r4, r4, #0x3
-
-	ldr r1, =S3C_MEMCTL_BASE
-	/* configure both SDRAM areas with 32 bit data bus width */
-	ldr r0, =((0x2 << 24) + (0x2 << 28))
-	str r0, [r1], #0x1c	/* post add register offset for bank6 */
-
-	/*
-	 * With the configuration we simply need to calculate an offset into
-	 * our table with the predefined SDRAM settings
-	 */
-	adr r0, SDRAMDATA
-	mov r2, #6*4		/* # of bytes per table entry */
-	mul r3, r4, r2
-	add r0, r0, r3		/* start address of the entry */
-
-	/*
-	 * store the table entry data into the registers
-	 */
-1:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	subs    r2, r2, #4
-	bne     1b
-
-/* TODO: Check if the second bank is populated, and switch it off if not */
-
-	mov pc, lr
-
-/*
- * we need 4 sets of memory settings per main CPU clock speed
- *
- * 400MHz main speed:
- * - 16 MiB in the first bank, maybe 16 MiB in the second bank (untested!)
- * - 32 MiB in the first bank, maybe 32 MiB in the second bank (CL=2)
- * - 64 MiB in the first bank, maybe 64 MiB in the second bank (CL=2)
- * - 128 MiB in the first bank, maybe 128 MiB in the second bank (untested!)
- *
- * Note: SDRAM clock runs at 100MHz
- */
-
-SDRAMDATA:
-/* --------------------------- 16 MiB @ 100MHz --------------------------- */
-	/*
-	 *  - MT = 11 (= sync dram type)
-	 *  - Trcd = 01 (= CL3)
-	 *  - SCAN = 00 (= 8 bit columns)
-	 */
-	.word ((0x3 << 15) + (0x1 << 2) + (0x0))
-	.word ((0x3 << 15) + (0x1 << 2) + (0x0))
-	/*
-	 * SDRAM refresh settings
-	 *  - REFEN = 1 (= refresh enabled)
-	 *  - TREFMD = 0 (= auto refresh)
-	 *  - Trp = 00 (= 2 RAS precharge clocks)
-	 *  - Tsrc = 11 (= 7 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
-	 *  - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = FIXME
-	 */
-	.word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x3 << 18) + 468)
-	/*
-	 * SDRAM banksize
-	 *  - BURST_EN = 0 (= burst mode disabled)
-	 *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
-	 *  - SCLK_EN = 1 (= clock active only during accesses)
-	 *  - BK67MAP = 010 (= 128MiB) FIXME?????
-	 */
-	.word ((0 << 7) + (1 << 5) + (1 << 4) + 2)
-	/*
-	 * SDRAM mode register
-	 * CL = 010 (= 2 clocks)
-	 */
-	.word (0x2 << 4)
-	.word (0x2 << 4)
-
-/* ------------- one or two banks with 64 MiB @ 100MHz -------------------- */
-
-	/*
-	 *  - MT = 11 (= sync dram type)
-	 *  - Trcd = 00 (= CL2)
-	 *  - SCAN = 01 (= 9 bit columns)
-	 */
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	/*
-	 * SDRAM refresh settings
-	 *  - REFEN = 1 (= refresh enabled)
-	 *  - TREFMD = 0 (= auto refresh)
-	 *  - Trp = 00 (= 2 RAS precharge clocks)
-	 *  - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
-	 *  - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489
-	 */
-	.word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489)
-	/*
-	 * SDRAM banksize
-	 *  - BURST_EN = 1 (= burst mode enabled)
-	 *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
-	 *  - SCLK_EN = 1 (= clock active only during accesses)
-	 *  - BK67MAP = 001 (= 64 MiB)
-	 */
-	.word ((1 << 7) + (1 << 5) + (1 << 4) + 1)
-	/*
-	 * SDRAM mode register
-	 * CL = 010 (= 2 clocks)
-	 */
-	.word (0x2 << 4)
-	.word (0x2 << 4)
-
-/* ------------- one or two banks with 32 MiB @ 100MHz -------------------- */
-
-	/*
-	 *  - MT = 11 (= sync dram type)
-	 *  - Trcd = 00 (= CL2)
-	 *  - SCAN = 01 (= 9 bit columns)
-	 */
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	/*
-	 * SDRAM refresh settings
-	 *  - REFEN = 1 (= refresh enabled)
-	 *  - TREFMD = 0 (= auto refresh)
-	 *  - Trp = 00 (= 2 RAS precharge clocks)
-	 *  - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
-	 *  - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489
-	 */
-	.word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489)
-	/*
-	 * SDRAM banksize
-	 *  - BURST_EN = 1 (= burst mode enabled)
-	 *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
-	 *  - SCLK_EN = 1 (= clock active only during accesses)
-	 *  - BK67MAP = 000 (= 32 MiB)
-	 */
-	.word ((1 << 7) + (1 << 5) + (1 << 4) + 0)
-	/*
-	 * SDRAM mode register
-	 * CL = 010 (= 2 clocks)
-	 */
-	.word (0x2 << 4)
-	.word (0x2 << 4)
-
-/* ------------ one or two banks with 128 MiB @ 100MHz -------------------- */
-
-	/*
-	 *  - MT = 11 (= sync dram type)
-	 *  - Trcd = 00 (= CL2)
-	 *  - SCAN = 01 (= 9 bit columns)
-	 */
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	/*
-	 * SDRAM refresh settings
-	 *  - REFEN = 1 (= refresh enabled)
-	 *  - TREFMD = 0 (= auto refresh)
-	 *  - Trp = 00 (= 2 RAS precharge clocks)
-	 *  - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
-	 *  - Refrsh = 2^11 + 1 - 100 * 7.5 = 2049 - FIXME = 1259
-	 */
-	.word ((0x1 << 23) + (0x0 << 22) + (0x1 << 20) + (0x3 << 18) + 1259)
-	/*
-	 * SDRAM banksize
-	 *  - BURST_EN = 0 (= burst mode disabled)
-	 *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
-	 *  - SCLK_EN = 1 (= clock active only during accesses)
-	 *  - BK67MAP = 010 (= 128MiB)
-	 */
-	.word (0x32)
-	/*
-	 * SDRAM mode register
-	 * CL = 010 (= 2 clocks)
-	 */
-	.word (0x2 << 4)
-	.word (0x2 << 4)
-
-/* ------------------------------------------------------------------------ */
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
-
-	bl arm_cpu_lowlevel_init
-
-	bl s3c24x0_disable_wd
-
-	/* skip everything here if we are already running from SDRAM */
-	cmp pc, #S3C_SDRAM_BASE
-	blo 1f
-	cmp pc, #S3C_SDRAM_END
-	bhs 1f
-
-	b out
-
-/* we are running from NOR or NAND/SRAM memory. Do further initialisation */
-1:
-	bl s3c24x0_pll_init
-
-	bl sdram_init
-
-#ifdef CONFIG_S3C_NAND_BOOT
-/* up to here we are running from the internal SRAM area */
-	bl s3c24x0_nand_boot
-#endif
-out:
-	mov r0, #S3C_SDRAM_BASE
-	mov r1, #SZ_32M
-	mov r2, #0
-	b barebox_arm_entry
diff --git a/arch/arm/boards/friendlyarm-mini2440/Kconfig b/arch/arm/boards/friendlyarm-mini2440/Kconfig
deleted file mode 100644
index 1037f7c77d..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/Kconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if MACH_MINI2440
-
-config MINI2440_VIDEO
-	bool
-	select VIDEO
-	select DRIVER_VIDEO_S3C24XX
-
-config MINI2440_VIDEO_N35
-	bool "Support N35 display (240x320)"
-	select MINI2440_VIDEO
-	help
-	  This adds support for NEC 3.5 inch TFT display,
-	  the most common one used with MINI2440 board.
-
-config MINI2440_VIDEO_A70
-	bool "Support A70 display (800x480)"
-	select MINI2440_VIDEO
-	help
-	  This adds support for Innolux 7.0 inch TFT display.
-
-config MINI2440_VIDEO_SVGA
-	bool "Support SVGA video adapter"
-	select MINI2440_VIDEO
-	help
-	  This adds support for MINI2440 SVGA (1024x768) video output adapter.
-
-config MINI2440_VIDEO_W35
-	bool "Support W35 display (320x240)"
-	select MINI2440_VIDEO
-	help
-	  This adds support for Sharp 3.5 inch TFT display.
-
-endif
diff --git a/arch/arm/boards/friendlyarm-mini2440/Makefile b/arch/arm/boards/friendlyarm-mini2440/Makefile
deleted file mode 100644
index 618828126c..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-
-obj-y += mini2440.o
-lwl-y += lowlevel_init.o
diff --git a/arch/arm/boards/friendlyarm-mini2440/config.h b/arch/arm/boards/friendlyarm-mini2440/config.h
deleted file mode 100644
index 86c78e54f6..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/config.h
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/**
- * @file
- * @brief Global defintions for the ARM S3C2440 based mini2440 CPU card
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/**
- * The external clock reference is a 12.00 MHz crystal
- */
-#define S3C24XX_CLOCK_REFERENCE 12000000
-
-/**
- * Define the main clock configuration to be used in register CLKDIVN
- *
- * We must limit the frequency of the connected SDRAMs with the clock ratio
- * setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 405Mhz:102MHz:51MHz
- */
-#define BOARD_SPECIFIC_CLKDIVN 0x05
-
-/**
- * Define the MPLL configuration to be used in register MPLLCON
- *
- * We want the MPLL to run at 405.0 MHz
- */
-#define BOARD_SPECIFIC_MPLL ((0x7f << 12) + (2 << 4) + 1)
-
-/**
- * Define the UPLL configuration to be used in register UPLLCON
- *
- * We want the UPLL to run at 48.0 MHz
- */
-#define BOARD_SPECIFIC_UPLL ((0x38 << 12) + (2 << 4) + 2)
-
-/*
- * Flash access timings
- * Tacls  = 0ns (but 20ns data setup time)
- * Twrph0 = 25ns (write) 35ns (read)
- * Twrph1 = 10ns (10ns data hold time)
- * Read cycle time = 50ns
- *
- * Assumed HCLK is 100MHz
- * Tacls = 1 (-> 20ns)
- * Twrph0 = 3 (-> 40ns)
- * Twrph1 = 1 (-> 20ns)
- * Cycle time = 80ns
- */
-#define MINI2440_TACLS 1
-#define MINI2440_TWRPH0 3
-#define MINI2440_TWRPH1 1
-
-/* needed in the generic NAND boot code only */
-#ifdef CONFIG_S3C_NAND_BOOT
-# define BOARD_DEFAULT_NAND_TIMING \
-	CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0, MINI2440_TWRPH1)
-#endif
-
-/*
- * Needed in the generic SDRAM boot code only
- *
- * SDRAM configuration
- * Two types of SDRAM devices are common on mini2440:
- * - Two devices of HY57V561620 to form 64 MiB in bank 6 only
- *   - http://friendlyarm.net/dl.php?file=HY57V561620.pdf
- * - Two devices of MT48LC16M16 to form 64 MiB in bank 6 only
- *   - http://friendlyarm.net/dl.php?file=MT48LC16M16.pdf
-
- * Most of the time the CPU is specified for 400 MHz only. As the CPU frequency
- * and the SDRAM frequency are fix coupled by 4:1, the SDRAM runs at HCLCK.
- * So, we need a 100 MHz timing setup with CL=2 for the SDRAMs.
- */
-
-/*
- * - ST7/WS7/DW7: reserved, this SDRAM bank is not used
- * - ST6/WS6/DW6: 32 bit data bus (for SDRAM usage)
- * - ST5/WS5/DW5: reserved, to be set by the board init code
- * - ST4/WS4/DW4: reserved, to be set by the board init code
- * - ST3/WS3/DW3: reserved, to be set by the board init code
- * - ST2/WS2/DW2: reserved, to be set by the board init code
- * - ST1/WS1/DW1: reserved, to be set by the board init code
- * - DW0: not to be changed
- */
-#define BOARD_SPECIFIC_BWSCON ((0x3 << 28) | (0x2 << 24) | 0x333330)
-/*
- *  - MT = 11 (= sync dram type)
- *  - Trcd = 00 (= CL2)
- *  - SCAN = 01 (= 9 bit columns)
- */
-#define BOARD_SPECIFIC_BANKCON6 ((0x3 << 15) + (0x0 << 2) + (0x1))
-#define BOARD_SPECIFIC_BANKCON7 0 /* disabled */
-/*
- * SDRAM refresh settings
- *  - REFEN = 1 (= refresh enabled)
- *  - TREFMD = 0 (= auto refresh)
- *  - Trp = 00 (= 2 RAS precharge clocks)
- *  - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
- *  - Refresh = 2^11 + 1 - 100 * 7.8 = 2049 - 780 = 1269
- */
-#define BOARD_SPECIFIC_REFRESH ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 1269)
-/*
- * SDRAM banksize
- *  - BURST_EN = 1 (= burst mode enabled)
- *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
- *  - SCLK_EN = 1 (= clock active only during accesses)
- *  - BK67MAP = 001 (= 64 MiB)
- */
-# define BOARD_SPECIFIC_BANKSIZE ((1 << 7) + (1 << 5) + (1 << 4) + 1)
-/*
- * SDRAM mode register
- * CL = 010 (= 2 clocks)
- */
-# define BOARD_SPECIFIC_MRSRB6 (0x2 << 4)
-# define BOARD_SPECIFIC_MRSRB7 0	/* not used */
-
-#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/friendlyarm-mini2440/env/boot/nand b/arch/arm/boards/friendlyarm-mini2440/env/boot/nand
deleted file mode 100644
index e0ef904432..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/env/boot/nand
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/sh
-
-global.bootm.image="/dev/nand0.kernel.bb"
-global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs"
diff --git a/arch/arm/boards/friendlyarm-mini2440/env/config-board b/arch/arm/boards/friendlyarm-mini2440/env/config-board
deleted file mode 100644
index 3e07a015b0..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/env/config-board
+++ /dev/null
@@ -1,16 +0,0 @@
-#!/bin/sh
-
-# board defaults, do not change in running system. Change /env/config
-# instead
-
-global.linux.bootargs.console="console=ttySAC0,115200"
-
-#
-# "mini2440" kernel parameter
-# 0 .. 9 = screen type
-# b = backlight enabled
-# t = touch enabled
-# c = camera enabled
-# Note: can be "minit2440= " if nothing of these components are connected
-#
-global.linux.bootargs.base="mini2440=6tb"
diff --git a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand b/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand
deleted file mode 100644
index b51104ad76..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-
-mtdparts="256k(nand0.barebox),128k(nand0.bareboxenv),1536k(nand0.kernel),-(nand0.root)"
-kernelname="nand"
-
-mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S b/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S
deleted file mode 100644
index b26efa12b0..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Low level initialization for the FriendlyARM mini2440 board
- */
-
-#include <config.h>
-#include <linux/sizes.h>
-#include <mach/s3c-iomap.h>
-#include <asm/barebox-arm-head.h>
-
-	.section ".text_bare_init.barebox_arm_reset_vector","ax"
-
-/* ------------------------------------------------------------------------ */
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
-	bl arm_cpu_lowlevel_init
-
-	bl s3c24x0_disable_wd
-
-	/* skip everything here if we are already running from SDRAM */
-	cmp pc, #S3C_SDRAM_BASE
-	blo 1f
-	cmp pc, #S3C_SDRAM_END
-	bhs 1f
-
-	b out
-
-/* we are running from NOR or NAND/SRAM memory. Do further initialisation */
-1:
-	bl s3c24x0_pll_init
-
-	bl s3c24x0_sdram_init
-
-#ifdef CONFIG_S3C_NAND_BOOT
-/* up to here we are running from the internal SRAM area */
-	bl s3c24x0_nand_boot
-#endif
-out:
-	mov r0, #S3C_SDRAM_BASE
-	mov r1, #SZ_32M
-	mov r2, #0
-	b barebox_arm_entry
diff --git a/arch/arm/boards/friendlyarm-mini2440/mini2440.c b/arch/arm/boards/friendlyarm-mini2440/mini2440.c
deleted file mode 100644
index 5933f664b5..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/mini2440.c
+++ /dev/null
@@ -1,341 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/*
- * Copyright (C) 2010 Marek Belisko <marek.belisko at open-nandra.com>
- *
- * Based on a9m2440.c board init by Juergen Beisert, Pengutronix
- */
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <generated/mach-types.h>
-#include <platform_data/eth-dm9000.h>
-#include <nand.h>
-#include <mci.h>
-#include <fb.h>
-#include <asm/armlinux.h>
-#include <asm/sections.h>
-#include <io.h>
-#include <gpio.h>
-#include <mach/bbu.h>
-#include <mach/iomux.h>
-#include <mach/s3c-iomap.h>
-#include <mach/devices-s3c24xx.h>
-#include <mach/s3c24xx-nand.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-mci.h>
-#include <mach/s3c24xx-fb.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-static struct s3c24x0_nand_platform_data nand_info = {
-	.nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
-							MINI2440_TWRPH1),
-	.flash_bbt = 1,	/* same as the kernel */
-};
-
-/*
- * dm9000 network controller onboard
- * Connected to CS line 4 and interrupt line EINT7,
- * data width is 16 bit
- * Area 1: Offset 0x300...0x303
- * Area 2: Offset 0x304...0x307
- */
-static struct dm9000_platform_data dm9000_data = {
-	.srom     = 1,
-};
-
-static struct s3c_mci_platform_data mci_data = {
-	.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED,
-	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
-	.gpio_detect = 232,	/* GPG8_GPIO */
-	.detect_invert = 0,
-};
-
-static struct fb_videomode s3c24x0_fb_modes[] = {
-#ifdef CONFIG_MINI2440_VIDEO_N35
-	{
-		.name		= "N35",
-		.refresh	= 60,
-		.xres		= 240,
-		.left_margin	= 21,
-		.right_margin	= 38,
-		.hsync_len	= 6,
-		.yres		= 320,
-		.upper_margin	= 4,
-		.lower_margin	= 4,
-		.vsync_len	= 2,
-		.pixclock	= 115913,
-		.sync		= FB_SYNC_USE_PWREN,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-#endif
-#ifdef CONFIG_MINI2440_VIDEO_A70
-	{
-		.name		= "A70",
-		.refresh	= 50,
-		.xres		= 800,
-		.left_margin	= 40,
-		.right_margin	= 40,
-		.hsync_len	= 48,
-		.yres		= 480,
-		.upper_margin	= 29,
-		.lower_margin	= 3,
-		.vsync_len	= 3,
-		.pixclock	= 41848,
-		.sync		= FB_SYNC_USE_PWREN | FB_SYNC_DE_HIGH_ACT,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-#endif
-#ifdef CONFIG_MINI2440_VIDEO_SVGA
-	{
-		.name		= "SVGA",
-		.refresh	= 24,
-		.xres		= 1024,
-		.left_margin	= 1,
-		.right_margin	= 2,
-		.hsync_len	= 2,
-		.yres		= 768,
-		.upper_margin	= 200,
-		.lower_margin	= 16,
-		.vsync_len	= 16,
-		.pixclock	= 40492,
-		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_DE_HIGH_ACT
-                                  /* | FB_SYNC_SWAP_HW */ /* FIXME maybe */ ,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-#endif
-#ifdef CONFIG_MINI2440_VIDEO_W35
-	{
-		.name		= "W35",
-		.refresh	= 60,
-		.xres		= 320,
-		.left_margin	= 68,
-		.right_margin	= 66,
-		.hsync_len	= 4,
-		.yres		= 240,
-		.upper_margin	= 4,
-		.lower_margin	= 4,
-		.vsync_len	= 9,
-		.pixclock	= 115913,
-		.sync		= FB_SYNC_USE_PWREN | FB_SYNC_CLK_INVERT,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-#endif
-};
-
-static struct s3c_fb_platform_data s3c24x0_fb_data = {
-	.mode_list		= s3c24x0_fb_modes,
-	.mode_cnt		= sizeof(s3c24x0_fb_modes) / sizeof(struct fb_videomode),
-	.bits_per_pixel		= 16,
-	.passive_display	= 0,
-};
-
-static const unsigned pin_usage[] = {
-	/* address bus, used by NOR, SDRAM */
-	GPA1_ADDR16,
-	GPA2_ADDR17,
-	GPA3_ADDR18,
-	GPA4_ADDR19,
-	GPA5_ADDR20,
-	GPA6_ADDR21,
-	GPA7_ADDR22,
-
-	GPA8_ADDR23_GPIO | GPIO_IN,
-	GPA9_ADDR24,	/* BA0 */
-	GPA10_ADDR25,	/* BA1 */
-	GPA11_ADDR26_GPIO | GPIO_IN,	/* not connected */
-
-	/* DM9000 requirements */
-	GPA15_NGCS4,
-	GPF7_EINT7,
-
-	/* de-activate the speaker */
-	GPB0_GPIO | GPIO_OUT | GPIO_VAL(0),
-
-	/* SD socket */
-	GPE5_SDCLK,
-	GPE6_SDCMD,
-	GPE7_SDDAT0,
-	GPE8_SDDAT1,
-	GPE9_SDDAT2,
-	GPE10_SDDAT3,
-	GPG8_GPIO | GPIO_IN,	/* change detection */
-	GPH8_GPIO | GPIO_IN,	/* write protection sense */
-
-	/* NAND requirements */
-	GPA17_CLE,
-	GPA18_ALE,
-	GPA19_NFWE,
-	GPA20_NFRE,
-	GPA21_NRSTOUT,
-	GPA22_NFCE,
-
-	/* Video out */
-	GPC0_LEND,
-	GPC1_VCLK,
-	GPC2_VLINE,
-	GPC3_VFRAME,
-	GPC4_VM,
-	GPC5_LPCOE,
-	GPC6_LPCREV,
-	GPC7_LPCREVB,
-	GPG4_LCD_PWREN,
-
-	GPC8_VD0,
-	GPC9_VD1,
-	GPC10_VD2,
-	GPC11_VD3,
-	GPC12_VD4,
-	GPC13_VD5,
-	GPC14_VD6,
-	GPC15_VD7,
-	GPD0_VD8,
-	GPD1_VD9,
-	GPD2_VD10,
-	GPD3_VD11,
-	GPD4_VD12,
-	GPD5_VD13,
-	GPD6_VD14,
-	GPD7_VD15,
-	GPD8_VD16,
-	GPD9_VD17,
-	GPD10_VD18,
-	GPD11_VD19,
-	GPD12_VD20,
-	GPD13_VD21,
-	GPD14_VD22,
-	GPD15_VD23,
-
-	/* K6 or CON12, pin 6, external pull up  */
-	GPG11_EINT19 | GPIO_IN,
-	/* K5 or CON12, pin 5*/
-	GPG7_EINT15 | GPIO_IN,
-	/* K4 or CON12, pin 4 */
-	GPG6_EINT14 | GPIO_IN,
-	/* K3 or CON12, pin 3 */
-	GPG5_EINT13 | GPIO_IN,
-	/* K2 or CON12, pin 2 */
-	GPG3_EINT11 | GPIO_IN,
-	/* K1 or CON12, pin 1, external pull up */
-	GPG0_EINT8 | GPIO_IN,
-
-	/* LED 1 1=off */
-	GPB5_GPIO | GPIO_OUT | GPIO_VAL(1),
-	/* LED 2 1=off */
-	GPB6_GPIO | GPIO_OUT | GPIO_VAL(1),
-	/* LED 3 1=off */
-	GPB7_GPIO | GPIO_OUT | GPIO_VAL(1),
-	/* LED 4 1=off */
-	GPB8_GPIO | GPIO_OUT | GPIO_VAL(1),
-
-	/* camera interface (ignore it) */
-	GPJ0_GPIO | GPIO_IN,
-	GPJ1_GPIO | GPIO_IN,
-	GPJ2_GPIO | GPIO_IN,
-	GPJ3_GPIO | GPIO_IN,
-	GPJ4_GPIO | GPIO_IN,
-	GPJ5_GPIO | GPIO_IN,
-	GPJ6_GPIO | GPIO_IN,
-	GPJ7_GPIO | GPIO_IN,
-	GPJ8_GPIO | GPIO_IN,
-	GPJ9_GPIO | GPIO_IN,
-	GPJ10_GPIO | GPIO_IN,
-	GPJ11_GPIO | GPIO_IN,
-	GPJ12_GPIO | GPIO_IN,
-
-	/* I2C bus */
-	GPE14_IICSCL,	/* external pull up */
-	GPE15_IICSDA,	/* external pull up */
-
-	GPA12_NGCS1,	/* CON5, pin 7 */
-	GPA13_NGCS2,	/* CON5, pin 8 */
-	GPA14_NGCS3,	/* CON5, pin 9 */
-	GPA16_NGCS5,	/* CON5, pin 10 */
-
-	/* UART2 (spare) */
-	GPH4_TXD1,
-	GPH5_RXD1,
-
-	/* UART3 (spare) */
-	GPH6_TXD2,
-	GPH7_RXD2,
-};
-
-static int mini2440_mem_init(void)
-{
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size());
-
-	return 0;
-}
-mem_initcall(mini2440_mem_init);
-
-static int mini2440_devices_init(void)
-{
-	uint32_t reg;
-	int i;
-
-	/* ----------- configure the access to the outer space ---------- */
-	for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
-		s3c_gpio_mode(pin_usage[i]);
-
-	reg = readl(S3C_BWSCON);
-
-	/* CS#4 to access the network controller */
-	reg &= ~0x000f0000;
-	reg |=  0x000d0000;	/* 16 bit */
-	writel(0x1f4c, S3C_BANKCON4);
-
-	writel(reg, S3C_BWSCON);
-
-	/* release the reset signal to external devices */
-	reg = readl(S3C_MISCCR);
-	reg |= 0x10000;
-	writel(reg, S3C_MISCCR);
-
-	s3c24xx_add_nand(&nand_info);
-
-	add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304,
-			  IORESOURCE_MEM_16BIT, &dm9000_data);
-#ifdef CONFIG_NAND
-	/* ----------- add some vital partitions -------- */
-	devfs_del_partition("self_raw");
-	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
-	dev_add_bb_dev("self_raw", "self0");
-
-	devfs_del_partition("env_raw");
-	devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
-	dev_add_bb_dev("env_raw", "env0");
-
-	s3c24x0_bbu_nand_register_handler();
-#endif
-	s3c24xx_add_mci(&mci_data);
-	s3c24xx_add_fb(&s3c24x0_fb_data);
-	s3c24xx_add_ohci();
-	armlinux_set_architecture(MACH_TYPE_MINI2440);
-
-	return 0;
-}
-
-device_initcall(mini2440_devices_init);
-
-static int mini2440_console_init(void)
-{
-	/*
-	 * configure the UART1 right now, as barebox will
-	 * start to send data immediately
-	 */
-	s3c_gpio_mode(GPH0_NCTS0);
-	s3c_gpio_mode(GPH1_NRTS0);
-	s3c_gpio_mode(GPH2_TXD0);
-	s3c_gpio_mode(GPH3_RXD0);
-
-	barebox_set_model("Friendlyarm mini2440");
-	barebox_set_hostname("mini2440");
-
-	s3c24xx_add_uart1();
-	return 0;
-}
-
-console_initcall(mini2440_console_init);
diff --git a/arch/arm/boards/friendlyarm-mini6410/Makefile b/arch/arm/boards/friendlyarm-mini6410/Makefile
deleted file mode 100644
index 2e6ea7aa7e..0000000000
--- a/arch/arm/boards/friendlyarm-mini6410/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-obj-y += mini6410.o
-lwl-y += lowlevel.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-friendlyarm-mini6410
diff --git a/arch/arm/boards/friendlyarm-mini6410/config.h b/arch/arm/boards/friendlyarm-mini6410/config.h
deleted file mode 100644
index 87b6ea4a29..0000000000
--- a/arch/arm/boards/friendlyarm-mini6410/config.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* FriendlyARM Mini6410 specific global settings */
-
-#ifndef _MINI6410_CONFIG_H_
-# define _MINI6410_CONFIG_H_
-
-#define S3C64XX_CLOCK_REFERENCE 12000000
-
-#endif /* _MINI6410_CONFIG_H_ */
diff --git a/arch/arm/boards/friendlyarm-mini6410/defaultenv-friendlyarm-mini6410/config b/arch/arm/boards/friendlyarm-mini6410/defaultenv-friendlyarm-mini6410/config
deleted file mode 100644
index 924d7b8cc7..0000000000
--- a/arch/arm/boards/friendlyarm-mini6410/defaultenv-friendlyarm-mini6410/config
+++ /dev/null
@@ -1,52 +0,0 @@
-#!/bin/sh
-
-machine=mini6410
-eth0.serverip=a.b.c.d.e
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d.e
-#eth0.netmask=a.b.c.d.e
-#eth0.gateway=a.b.c.d.e
-#eth0.ethaddr=
-
-# can be either 'nfs', 'tftp' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-${machine}.${rootfs_type}
-
-# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
-kernelimage=zImage-${machine}
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
-
-if [ -n $user ]; then
-	kernelimage="${user}"-"${kernelimage}"
-	nfsroot="${eth0.serverip}:/home/${user}/nfsroot/${machine}"
-	rootfsimage="${user}"-"${rootfsimage}"
-else
-	nfsroot="${eth0.serverip}:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-#
-# "mini6410" kernel parameter
-# 0 .. 9 = screen type
-# i = touchscreen with propritary FriendlyARM protocol
-# Note: can be "minit6410= " if nothing of these components are connected
-#
-bootargs="console=ttySAC0,115200 mini6410=0"
-
-nand_device="nand"
-nand_parts="256k(barebox),128k(bareboxenv),1536k(kernel),-(root)"
-rootfs_mtdblock_nand=3
diff --git a/arch/arm/boards/friendlyarm-mini6410/lowlevel.c b/arch/arm/boards/friendlyarm-mini6410/lowlevel.c
deleted file mode 100644
index dfb69d2272..0000000000
--- a/arch/arm/boards/friendlyarm-mini6410/lowlevel.c
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/s3c-iomap.h>
-
-void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	arm_cpu_lowlevel_init();
-	barebox_arm_entry(S3C_SDRAM_BASE, SZ_128M, NULL);
-}
diff --git a/arch/arm/boards/friendlyarm-mini6410/mini6410.c b/arch/arm/boards/friendlyarm-mini6410/mini6410.c
deleted file mode 100644
index 3f5e8ca2a3..0000000000
--- a/arch/arm/boards/friendlyarm-mini6410/mini6410.c
+++ /dev/null
@@ -1,302 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2012 Juergen Beisert
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <platform_data/eth-dm9000.h>
-#include <gpio.h>
-#include <envfs.h>
-#include <generated/mach-types.h>
-#include <asm/armlinux.h>
-#include <mach/s3c-iomap.h>
-#include <mach/devices-s3c64xx.h>
-#include <mach/s3c-generic.h>
-#include <mach/iomux.h>
-
-/*
- * dm9000 network controller onboard
- * Connected to CS line 1 and interrupt line EINT7,
- * data width is 16 bit
- * Area 1: Offset 0x300...0x301
- * Area 2: Offset 0x304...0x305
- */
-static struct dm9000_platform_data dm9000_data = {
-	.srom = 0,	/* no serial ROM for the ethernet address */
-};
-
-static const unsigned pin_usage[] = {
-	/* UART2 (spare, 3,3 V TTL level only) */
-	GPA4_RXD1 | ENABLE_PU,
-	GPA5_TXD1,
-	GPA6_NCTS1 | ENABLE_PU,
-	GPA7_NRTS1,
-	/* UART3 (spare, 3,3 V TTL level only) */
-	GPB0_RXD2 | ENABLE_PU,
-	GPB1_TXD2,
-	/* UART4 (spare, 3,3 V TTL level only) */
-	GPB2_RXD3 | ENABLE_PU,
-	GPB3_TXD3,
-
-	GPB4_GPIO | GPIO_IN | ENABLE_PU,
-
-	/* I2C bus */
-	GPB5_IIC0_SCL,	/* external PU */
-	GPB6_IIC0_SDA,	/* external PU */
-
-	GPC0_SPI0_MISO | ENABLE_PU,
-	GPC1_SPI0_CLK,
-	GPC2_SPI0_MOSI,
-	GPC3_SPI0_NCS,
-
-	GPC4_SPI1_MISO | ENABLE_PU,
-	GPC5_SPI1_CLK,
-	GPC6_SPI1_MOSI,
-	GPC7_SPI1_NCS,
-
-	GPD0_AC97_BITCLK,
-	GPD1_AC97_NRST,
-	GPD2_AC97_SYNC,
-	GPD3_AC97_SDI | ENABLE_PU,
-	GPD4_AC97_SDO,
-
-	GPE0_GPIO | GPIO_OUT | GPIO_VAL(0), /* LCD backlight off */
-	GPE1_GPIO | GPIO_IN | ENABLE_PU,
-	GPE2_GPIO | GPIO_IN | ENABLE_PU,
-	GPE3_GPIO | GPIO_IN | ENABLE_PU,
-	GPE4_GPIO | GPIO_IN | ENABLE_PU,
-
-	/* keep all camera signals at reasonable values */
-	GPF0_GPIO | GPIO_IN | ENABLE_PU,
-	GPF1_GPIO | GPIO_IN | ENABLE_PU,
-	GPF2_GPIO | GPIO_IN | ENABLE_PU,
-	GPF3_GPIO | GPIO_IN | ENABLE_PU,
-	GPF4_GPIO | GPIO_IN | ENABLE_PU,
-	GPF5_GPIO | GPIO_IN | ENABLE_PU,
-	GPF6_GPIO | GPIO_IN | ENABLE_PU,
-	GPF7_GPIO | GPIO_IN | ENABLE_PU,
-	GPF8_GPIO | GPIO_IN | ENABLE_PU,
-	GPF9_GPIO | GPIO_IN | ENABLE_PU,
-	GPF10_GPIO | GPIO_IN | ENABLE_PU,
-	GPF11_GPIO | GPIO_IN | ENABLE_PU,
-	GPF12_GPIO | GPIO_IN | ENABLE_PU,
-	GPF13_GPIO | GPIO_OUT | GPIO_VAL(0), /* USB power off */
-#if 0
-	GPF14_CLKOUT, /* for testing purposes, but very noisy */
-#else
-	GPF14_GPIO | GPIO_OUT | GPIO_VAL(0), /* Buzzer off */
-#endif
-	GPF15_GPIO | GPIO_OUT | GPIO_VAL(0), /* Backlight PWM inactive */
-
-	/* SD card slot (all signals have external 10k PU) */
-	GPG0_MMC0_CLK,
-	GPG1_MMC0_CMD,
-	GPG2_MMC0_DAT0,
-	GPG3_MMC0_DAT1,
-	GPG4_MMC0_DAT2,
-	GPG5_MMC0_DAT3,
-	GPG6_MMC0_NCD,
-
-	/* SDIO slot (all used signals have external PU) */
-	GPH0_GPIO | GPIO_IN,	/* CLK */
-	GPH1_GPIO | GPIO_IN,	/* CMD */
-	GPH2_GPIO | GPIO_IN,	/* DAT0 */
-	GPH3_GPIO | GPIO_IN,	/* DAT1 */
-	GPH4_GPIO | GPIO_IN,	/* DAT2 */
-	GPH5_GPIO | GPIO_IN,	/* DAT3 */
-	GPH6_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
-	GPH7_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
-	GPH8_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
-	GPH9_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
-
-	/* as long as we are not using the LCD controller, disable the pins */
-	GPI0_GPIO | GPIO_IN | ENABLE_PD,
-	GPI1_GPIO | GPIO_IN | ENABLE_PD,
-	GPI2_GPIO | GPIO_IN | ENABLE_PD,
-	GPI3_GPIO | GPIO_IN | ENABLE_PD,
-	GPI4_GPIO | GPIO_IN | ENABLE_PD,
-	GPI5_GPIO | GPIO_IN | ENABLE_PD,
-	GPI6_GPIO | GPIO_IN | ENABLE_PD,
-	GPI7_GPIO | GPIO_IN | ENABLE_PD,
-	GPI8_GPIO | GPIO_IN | ENABLE_PD,
-	GPI9_GPIO | GPIO_IN | ENABLE_PD,
-	GPI10_GPIO | GPIO_IN | ENABLE_PD,
-	GPI11_GPIO | GPIO_IN | ENABLE_PD,
-	GPI12_GPIO | GPIO_IN | ENABLE_PD,
-	GPI13_GPIO | GPIO_IN | ENABLE_PD,
-	GPI14_GPIO | GPIO_IN | ENABLE_PD,
-	GPI15_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ0_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ1_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ2_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ3_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ4_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ5_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ6_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ7_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ8_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ9_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ10_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ11_GPIO | GPIO_IN | ENABLE_PD,
-
-	GPK0_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK1_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK2_GPIO | GPIO_IN,
-	GPK3_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK4_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #1 (high = LED off) */
-	GPK5_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #2 (high = LED off) */
-	GPK6_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #3 (high = LED off) */
-	GPK7_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #4 (high = LED off) */
-	GPK8_GPIO | GPIO_IN, 			/* (external PU) */
-	GPK9_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK10_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK11_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK12_GPIO | GPIO_IN,			/* OCT_DET */
-	GPK13_GPIO | GPIO_IN,			/* WIFI power (external PU) */
-	GPK14_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK15_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-
-	GPL0_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL1_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL2_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL3_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL4_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL5_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL6_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL7_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL8_GPIO | GPIO_IN,			/* EINT16 (external PU) */
-	GPL9_GPIO | GPIO_IN | ENABLE_PU,	/* EINT17 */
-	GPL10_GPIO | GPIO_IN | ENABLE_PU,	/* EINT18 */
-	GPL11_GPIO | GPIO_IN,			/* EINT19 + K7 (external PU) */
-	GPL12_GPIO | GPIO_IN,			/* EINT20 + K6 (external PU) */
-	GPL13_GPIO | GPIO_IN,			/* SD0 WP (external PU) */
-	GPL14_GPIO | GPIO_IN,			/* SD1 WP (external PU) */
-
-	GPM0_GPIO | GPIO_IN,			/* (external PU) */
-	GPM1_GPIO | GPIO_IN,			/* (external PU) */
-	GPM2_GPIO | GPIO_IN,			/* (external PU) */
-	GPM3_GPIO | GPIO_IN,			/* (external PU) */
-	GPM4_GPIO | GPIO_IN,			/* (external PU) */
-	GPM5_GPIO | GPIO_IN,			/* (external PU) */
-
-	GPN0_GPIO | GPIO_IN,			/* EINT0 (external PU) */
-	GPN1_GPIO | GPIO_IN,			/* EINT1 (external PU) */
-	GPN2_GPIO | GPIO_IN,			/* EINT2 (external PU) */
-	GPN3_GPIO | GPIO_IN,			/* EINT3 (external PU) */
-	GPN4_GPIO | GPIO_IN,			/* EINT4 (external PU) */
-	GPN5_GPIO | GPIO_IN,			/* EINT5 (external PU) */
-	GPN6_GPIO | GPIO_IN,			/* EINT6 (external PU) */
-	GPN7_GPIO | GPIO_IN | ENABLE_PU,	/* EINT7 DM9000 interrupt */
-	GPN8_GPIO | GPIO_IN,			/* EINT8 USB detect (external PU) */
-	GPN9_GPIO | GPIO_IN,			/* EINT9 (external PU) */
-	GPN10_GPIO | GPIO_IN,			/* SD1 CD (external PU) */
-	GPN11_GPIO | GPIO_IN,			/* EINT11 (external PU) */
-	GPN12_GPIO | GPIO_IN,			/* EINT12 IR in (external PU) */
-	GPN13_GPIO | GPIO_IN,			/* BOOT0/EINT13 (externally fixed) */
-	GPN14_GPIO | GPIO_IN,			/* BOOT1/EINT14 (externally fixed) */
-	GPN15_GPIO | GPIO_IN,			/* BOOT2/EINT15 (externally fixed) */
-
-	GPO0_NCS2,				/* NAND */
-	GPO1_NCS3,				/* NAND */
-	GPO2_NCS4,				/* CON5 */
-	GPO3_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO4_GPIO | GPIO_IN | ENABLE_PU,	/* CON5 pin 8 */
-	GPO5_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO6_ADDR6,				/* CON5 */
-	GPO7_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO8_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO9_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO10_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO11_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO12_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO13_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO14_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO15_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-
-	GPP0_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP1_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP2_NWAIT | ENABLE_PU,			/* CON5 */
-	GPP3_FALE,				/* NAND */
-	GPP4_FCLE,				/* NAND */
-	GPP5_FWE,				/* NAND */
-	GPP6_FRE,				/* NAND */
-	GPP7_RNB,				/* NAND (external PU) */
-	GPP8_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP9_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP10_GPIO | GPIO_IN,			/* (external PU) */
-	GPP11_GPIO | GPIO_IN,			/* (external PU) */
-	GPP12_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP13_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP14_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-
-	GPQ0_GPIO | GPIO_IN | ENABLE_PU,	/* not used as LADDR18 */
-	GPQ1_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ2_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ3_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ4_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ5_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ6_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ7_GPIO | GPIO_IN | ENABLE_PU,	/* not used as LADDR17 */
-	GPQ8_GPIO | GPIO_IN | ENABLE_PU,	/* not used as LADDR16 */
-};
-
-static int mini6410_mem_init(void)
-{
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c6410_get_memory_size());
-
-	return 0;
-}
-mem_initcall(mini6410_mem_init);
-
-static const struct s3c6410_chipselect dm900_cs = {
-	.adr_setup_t = 0,
-	.access_setup_t = 0,
-	.access_t = 20,
-	.cs_hold_t = 3,
-	.adr_hold_t = 20, /* CS must be de-asserted for at least 20 ns */
-	.width = 16,
-};
-
-static void mini6410_setup_dm9000_cs(void)
-{
-	s3c6410_setup_chipselect(1, &dm900_cs);
-}
-
-static int mini6410_devices_init(void)
-{
-	int i;
-
-	/* ----------- configure the access to the outer space ---------- */
-	for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
-		s3c_gpio_mode(pin_usage[i]);
-
-	mini6410_setup_dm9000_cs();
-	add_dm9000_device(0, S3C_CS1_BASE + 0x300, S3C_CS1_BASE + 0x304,
-				IORESOURCE_MEM_16BIT, &dm9000_data);
-
-	armlinux_set_architecture(MACH_TYPE_MINI6410);
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_friendlyarm_mini6410);
-
-	return 0;
-}
-
-device_initcall(mini6410_devices_init);
-
-static int mini6410_console_init(void)
-{
-	s3c_gpio_mode(GPA0_RXD0 | ENABLE_PU);
-	s3c_gpio_mode(GPA1_TXD0);
-	s3c_gpio_mode(GPA2_NCTS0 | ENABLE_PU);
-	s3c_gpio_mode(GPA3_NRTS0);
-
-	barebox_set_model("Friendlyarm mini6410");
-	barebox_set_hostname("mini6410");
-
-	s3c64xx_add_uart1();
-
-	return 0;
-}
-
-console_initcall(mini6410_console_init);
diff --git a/arch/arm/boards/friendlyarm-tiny210/Makefile b/arch/arm/boards/friendlyarm-tiny210/Makefile
deleted file mode 100644
index d026a7ed47..0000000000
--- a/arch/arm/boards/friendlyarm-tiny210/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-obj-y += tiny210.o
-lwl-y += lowlevel.o
diff --git a/arch/arm/boards/friendlyarm-tiny210/config.h b/arch/arm/boards/friendlyarm-tiny210/config.h
deleted file mode 100644
index 7437e6bddd..0000000000
--- a/arch/arm/boards/friendlyarm-tiny210/config.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define S5PCXX_CLOCK_REFERENCE 24000000
-
-#define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
-
-#define BOARD_APLL_VAL	set_pll(0x7d, 0x3, 0x1)
-#define BOARD_MPLL_VAL	set_pll(0x29b, 0xc, 0x1)
-#define BOARD_EPLL_VAL	set_pll(0x60, 0x6, 0x2)
-#define BOARD_VPLL_VAL	set_pll(0x6c, 0x6, 0x3)
-
-#define BOARD_CLK_DIV0_MASK	0xFFFFFFFF
-#define BOARD_CLK_DIV0_VAL	0x14131440
-#define BOARD_APLL_LOCKTIME	0x2cf
-
-#define S5P_DRAM_WR	3
-#define S5P_DRAM_CAS	4
-#define DMC_TIMING_AREF	0x00000618
-#define DMC_TIMING_ROW	0x2B34438A
-#define DMC_TIMING_DATA	0x24240000
-#define DMC_TIMING_PWR	0x0BDC0343
diff --git a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c
deleted file mode 100644
index d79661b222..0000000000
--- a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: 2012 Alexey Galakhov
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <io.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/sections.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-clocks.h>
-#include <mach/s3c-generic.h>
-
-#define IRAM_CODE_BASE		0xD0020010
-
-/* Tiny210 has 4 leds numbered from 0 to 3 at GPJ2 */
-static inline void __bare_init debug_led(int led, bool state)
-{
-	uint32_t r;
-	/* GPJ2CON: mode 0001=output */
-	r = readl(0xE0200280);
-	r &= ~(0xF << (4 * led));
-	r |=  (0x1 << (4 * led));
-	writel(r, 0xE0200280);
-	/* GPJ2DAT: active low */
-	r = readl(0xE0200284);
-	r &= ~(1 << led);
-	r |= (state ? 0 : 1) << led;
-	writel(r, 0xE0200284);
-}
-
-/*
- * iROM boot from MMC
- * TODO: replace this by native boot
- */
-
-#define ADDR_V210_SDMMC_BASE	0xD0037488
-#define ADDR_CopySDMMCtoMem	0xD0037F98
-
-static int __bare_init s5p_irom_load_mmc(void *dest, uint32_t start_block,
-					 uint16_t block_count)
-{
-	typedef uint32_t (*func_t) (int32_t, uint32_t, uint16_t, uint32_t*, int8_t);
-	uint32_t chbase = readl(ADDR_V210_SDMMC_BASE);
-	func_t func = (func_t)readl(ADDR_CopySDMMCtoMem);
-	int chan = (chbase - 0xEB000000) >> 20;
-	if (chan != 0 && chan != 2)
-		return 0;
-	return func(chan, start_block, block_count, (uint32_t*)dest, 0) ? 1 : 0;
-}
-
-static __bare_init __naked void jump_sdram(unsigned long offset)
-{
-	__asm__ __volatile__ (
-			"sub lr, lr, %0;"
-			"mov pc, lr;" : : "r"(offset)
-			);
-}
-
-static __bare_init bool load_stage2(void *dest, size_t size)
-{
-	/* TODO add other ways to boot */
-	return s5p_irom_load_mmc(dest, 1, (size+ 511) / 512);
-}
-
-void __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	arm_cpu_lowlevel_init();
-
-#ifdef CONFIG_S3C_PLL_INIT
-	s5p_init_pll();
-#endif
-
-	debug_led(0, 1);
-
-	if (get_pc() < IRAM_CODE_BASE) /* Are we running from iRAM? */
-		/* No, we don't. */
-		goto boot;
-
-	s5p_init_dram_bank_ddr2(S5P_DMC0_BASE, 0x20E00323, 0, 0);
-
-	debug_led(1, 1);
-
-	if (! load_stage2((void*)(_text - 16),
-				barebox_image_size + 16)) {
-		debug_led(3, 1);
-		while (1) { } /* hang */
-	}
-
-	debug_led(2, 1);
-
-	jump_sdram(IRAM_CODE_BASE - (unsigned long)_text);
-
-	debug_led(1, 0);
-
-boot:
-	barebox_arm_entry(S3C_SDRAM_BASE, SZ_256M, NULL);
-}
diff --git a/arch/arm/boards/friendlyarm-tiny210/tiny210.c b/arch/arm/boards/friendlyarm-tiny210/tiny210.c
deleted file mode 100644
index c47f488207..0000000000
--- a/arch/arm/boards/friendlyarm-tiny210/tiny210.c
+++ /dev/null
@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/*
- * Copyright (C) 2012 Alexey Galakhov
- * Based on Mini6410 code by Juergen Beisert
- *
- * Copyright (C) 2012 Juergen Beisert, Pengutronix
- *
- * In some ways inspired by code
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger at sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller at elsoft.ch>
- */
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <linux/sizes.h>
-#include <generated/mach-types.h>
-#include <gpio.h>
-#include <led.h>
-#include <io.h>
-#include <nand.h>
-#include <asm/armlinux.h>
-#include <mach/iomux.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-clocks.h>
-#include <mach/s3c-generic.h>
-
-static struct gpio_led leds[] = {
-	{
-		.gpio = GPJ20,
-		.led = {
-			.name = "led1",
-		}
-	}, {
-		.gpio = GPJ21,
-		.led = {
-			.name = "led2",
-		}
-	}, {
-		.gpio = GPJ22,
-		.led = {
-			.name = "led3",
-		}
-	}, {
-		.gpio = GPJ23,
-		.led = {
-			.name = "led4",
-		}
-	}
-};
-
-static int tiny210_mem_init(void)
-{
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s5p_get_memory_size());
-	return 0;
-}
-mem_initcall(tiny210_mem_init);
-
-static int tiny210_console_init(void)
-{
-	/*
-	 * configure the UART1 right now, as barebox will
-	 * start to send data immediately
-	 */
-	s3c_gpio_mode(GPA00_RXD0 | ENABLE_PU);
-	s3c_gpio_mode(GPA01_TXD0);
-	s3c_gpio_mode(GPA02_NCTS0 | ENABLE_PU);
-	s3c_gpio_mode(GPA03_NRTS0);
-
-	barebox_set_model("Friendlyarm tiny210");
-	barebox_set_hostname("tiny210");
-
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL,
-			   S3C_UART1_BASE, S3C_UART1_SIZE,
-			   IORESOURCE_MEM, NULL);
-	return 0;
-}
-console_initcall(tiny210_console_init);
-
-static int tiny210_devices_init(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(leds); i++) {
-		leds[i].active_low = 1;
-		gpio_direction_output(leds[i].gpio, leds[i].active_low);
-		led_gpio_register(&leds[i]);
-	}
-
-	led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led);
-
-	armlinux_set_architecture(MACH_TYPE_MINI210);
-
-	return 0;
-}
-device_initcall(tiny210_devices_init);
diff --git a/arch/arm/boards/friendlyarm-tiny6410/Kconfig b/arch/arm/boards/friendlyarm-tiny6410/Kconfig
deleted file mode 100644
index 1283b8e7d9..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/Kconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if MACH_TINY6410
-
-choice
-	prompt "FriendlyARM Tiny6410 baseboard"
-	help
-	  Since the Tiny6410 is a CPU card only, it requires a basebord to make
-	  it work. Select here the baseboard Barebox should expect and
-	  configure.
-
-config MACH_TINY6410_FA
-	bool
-	select HAS_DM9000
-	prompt "FA development platform"
-	help
-	  FriendlyARM's Tiny6410 evaluation board.
-
-endchoice
-
-endif
diff --git a/arch/arm/boards/friendlyarm-tiny6410/Makefile b/arch/arm/boards/friendlyarm-tiny6410/Makefile
deleted file mode 100644
index f0b868d67f..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-obj-y += tiny6410.o
-lwl-y += lowlevel.o
-lwl-$(CONFIG_MACH_TINY6410_FA) += development-board.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-friendlyarm-tiny6410
diff --git a/arch/arm/boards/friendlyarm-tiny6410/config.h b/arch/arm/boards/friendlyarm-tiny6410/config.h
deleted file mode 100644
index 22692a3025..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/config.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* FriendlyARM Tiny6410 specific global settings */
-
-#ifndef _TINY6410_CONFIG_H_
-# define _TINY6410_CONFIG_H_
-
-#define S3C64XX_CLOCK_REFERENCE 12000000
-
-#endif /* _TINY6410_CONFIG_H_ */
diff --git a/arch/arm/boards/friendlyarm-tiny6410/defaultenv-friendlyarm-tiny6410/config b/arch/arm/boards/friendlyarm-tiny6410/defaultenv-friendlyarm-tiny6410/config
deleted file mode 100644
index f38535be48..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/defaultenv-friendlyarm-tiny6410/config
+++ /dev/null
@@ -1,52 +0,0 @@
-#!/bin/sh
-
-machine=tiny6410
-eth0.serverip=a.b.c.d.e
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d.e
-#eth0.netmask=a.b.c.d.e
-#eth0.gateway=a.b.c.d.e
-#eth0.ethaddr=
-
-# can be either 'nfs', 'tftp' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-${machine}.${rootfs_type}
-
-# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
-kernelimage=zImage-${machine}
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
-
-if [ -n $user ]; then
-	kernelimage="${user}"-"${kernelimage}"
-	nfsroot="${eth0.serverip}:/home/${user}/nfsroot/${machine}"
-	rootfsimage="${user}"-"${rootfsimage}"
-else
-	nfsroot="${eth0.serverip}:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-#
-# "tiny6410" kernel parameter
-# 0 .. 9 = screen type
-# i = touchscreen with propritary FriendlyARM protocol
-# Note: can be "tiny6410= " if nothing of these components are connected
-#
-bootargs="console=ttySAC0,115200 tiny6410=0"
-
-nand_device="nand"
-nand_parts="256k(barebox),128k(bareboxenv),1536k(kernel),-(root)"
-rootfs_mtdblock_nand=3
diff --git a/arch/arm/boards/friendlyarm-tiny6410/development-board.c b/arch/arm/boards/friendlyarm-tiny6410/development-board.c
deleted file mode 100644
index 69c9768405..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/development-board.c
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2012 Juergen Beisert
-
-/*
- * The FriendlyARM's Tiny6410 evaluation board comes with all connectors and
- * devices to make the Tiny6410 CPU card work. This includes:
- *
- * - the DM9000 network controller
- * - USB/MCI connectors
- * - display connector
- */
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <gpio.h>
-#include <platform_data/eth-dm9000.h>
-#include <mach/devices-s3c64xx.h>
-#include <mach/s3c-generic.h>
-#include <mach/iomux.h>
-
-#include "tiny6410.h"
-
-/*
- * dm9000 network controller onboard
- * Connected to CS line 1 and interrupt line EINT7,
- * data width is 16 bit
- * Area 1: Offset 0x300...0x301
- * Area 2: Offset 0x304...0x305
- */
-static struct dm9000_platform_data dm9000_data = {
-	.srom = 0,	/* no serial ROM for the ethernet address */
-};
-
-static const struct s3c6410_chipselect dm900_cs = {
-	.adr_setup_t = 0,
-	.access_setup_t = 0,
-	.access_t = 20,
-	.cs_hold_t = 3,
-	.adr_hold_t = 20, /* CS must be de-asserted for at least 20 ns */
-	.width = 16,
-};
-
-static void tiny6410evk_setup_dm9000_cs(void)
-{
-	s3c6410_setup_chipselect(1, &dm900_cs);
-}
-
-static const unsigned tiny6410evk_pin_usage[] = {
-	/* UART1 (V24) */
-	GPA4_RXD1 | ENABLE_PU,
-	GPA5_TXD1,
-	GPA6_NCTS1 | ENABLE_PU,
-	GPA7_NRTS1,
-	/* UART2 (V24) */
-	GPB0_RXD2 | ENABLE_PU,
-	GPB1_TXD2,
-	/* UART3 (spare, 3,3 V TTL level only) */
-	GPB2_RXD3 | ENABLE_PU,
-	GPB3_TXD3,
-};
-
-static int tiny6410evk_devices_init(void)
-{
-	int i;
-
-	/* init CPU card specific devices first */
-	tiny6410_init("FA EVK");
-
-	/* ----------- configure the access to the outer space ---------- */
-	for (i = 0; i < ARRAY_SIZE(tiny6410evk_pin_usage); i++)
-		s3c_gpio_mode(tiny6410evk_pin_usage[i]);
-
-	tiny6410evk_setup_dm9000_cs();
-	add_dm9000_device(0, S3C_CS1_BASE + 0x300, S3C_CS1_BASE + 0x304,
-				IORESOURCE_MEM_16BIT, &dm9000_data);
-	return 0;
-}
-device_initcall(tiny6410evk_devices_init);
-
-static int tiny6410evk_console_init(void)
-{
-	/* note: UART0 has no RTS/CTS connected */
-	s3c_gpio_mode(GPA0_RXD0 | ENABLE_PU);
-	s3c_gpio_mode(GPA1_TXD0);
-
-	barebox_set_model("Friendlyarm tiny6410");
-	barebox_set_hostname("tiny6410");
-
-	s3c64xx_add_uart1();
-
-	return 0;
-}
-console_initcall(tiny6410evk_console_init);
diff --git a/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c b/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c
deleted file mode 100644
index dfb69d2272..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/s3c-iomap.h>
-
-void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	arm_cpu_lowlevel_init();
-	barebox_arm_entry(S3C_SDRAM_BASE, SZ_128M, NULL);
-}
diff --git a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c
deleted file mode 100644
index a1126b7893..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2012 Juergen Beisert
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <gpio.h>
-#include <generated/mach-types.h>
-#include <asm/armlinux.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-#include <mach/iomux.h>
-
-#include "tiny6410.h"
-
-static const unsigned tiny6410_pin_usage[] = {
-	/* UART0 */
-	GPA2_GPIO | GPIO_IN | ENABLE_PU, /* CTS not connected */
-	GPA3_GPIO | GPIO_IN | ENABLE_PU, /* RTS not connected */
-
-	/* local bus' D0 ... D15 are always active */
-	/* local bus' A0...A5 are always active */
-
-	/* internal NAND memory */
-	GPO0_NCS2,	/* NAND's first chip select line */
-	/* NAND's second chip select line, not used */
-	GPO1_GPIO | GPIO_OUT | GPIO_VAL(1),
-	GPP3_FALE,
-	GPP4_FCLE,
-	GPP5_FWE,
-	GPP6_FRE,
-	GPP7_RNB, /* external pull-up */
-
-	GPF13_GPIO  | GPIO_OUT | GPIO_VAL(0), /* OTG power supply, 0 = off */
-
-	/* nowhere connected */
-	GPO2_GPIO | GPIO_IN | ENABLE_PU,
-	GPO3_GPIO | GPIO_IN | ENABLE_PU,
-	GPO4_GPIO | GPIO_IN | ENABLE_PU,
-	GPO5_GPIO | GPIO_IN | ENABLE_PU,
-
-	/* local bus address lines 6...15 are nowhere connected */
-	GPO6_GPIO | GPIO_IN | ENABLE_PU,
-	GPO7_GPIO | GPIO_IN | ENABLE_PU,
-	GPO8_GPIO | GPIO_IN | ENABLE_PU,
-	GPO9_GPIO | GPIO_IN | ENABLE_PU,
-	GPO10_GPIO | GPIO_IN | ENABLE_PU,
-	GPO11_GPIO | GPIO_IN | ENABLE_PU,
-	GPO12_GPIO | GPIO_IN | ENABLE_PU,
-	GPO13_GPIO | GPIO_IN | ENABLE_PU,
-	GPO14_GPIO | GPIO_IN | ENABLE_PU,
-	GPO15_GPIO | GPIO_IN | ENABLE_PU,
-};
-
-static int tiny6410_mem_init(void)
-{
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c6410_get_memory_size());
-
-	return 0;
-}
-mem_initcall(tiny6410_mem_init);
-
-void tiny6410_init(const char *bb_name)
-{
-	int i;
-
-	/* ----------- configure the access to the outer space ---------- */
-	for (i = 0; i < ARRAY_SIZE(tiny6410_pin_usage); i++)
-		s3c_gpio_mode(tiny6410_pin_usage[i]);
-
-	armlinux_set_architecture(MACH_TYPE_TINY6410);
-}
diff --git a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h
deleted file mode 100644
index bbe8877ca0..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/* to be called by the base board */
-void tiny6410_init(const char*);
diff --git a/arch/arm/configs/a9m2410_defconfig b/arch/arm/configs/a9m2410_defconfig
deleted file mode 100644
index ea70a121af..0000000000
--- a/arch/arm/configs/a9m2410_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_ARCH_S3C24xx=y
-CONFIG_S3C_NAND_BOOT=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_BAUDRATE=38400
-CONFIG_GLOB=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/a9m2410/env"
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_FLASH=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_SMC91111=y
-# CONFIG_SPI is not set
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/a9m2440_defconfig b/arch/arm/configs/a9m2440_defconfig
deleted file mode 100644
index 5843d29d7f..0000000000
--- a/arch/arm/configs/a9m2440_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-CONFIG_ARCH_S3C24xx=y
-CONFIG_MACH_A9M2440=y
-CONFIG_S3C_SDRAM_INIT=y
-CONFIG_S3C_NAND_BOOT=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_BAUDRATE=38400
-CONFIG_GLOB=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/a9m2440/env"
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_FLASH=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_SMC91111=y
-# CONFIG_SPI is not set
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/friendlyarm_mini2440_defconfig b/arch/arm/configs/friendlyarm_mini2440_defconfig
deleted file mode 100644
index 21c931ca05..0000000000
--- a/arch/arm/configs/friendlyarm_mini2440_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-CONFIG_TEXT_BASE=0x33e00000
-CONFIG_ARCH_S3C24xx=y
-CONFIG_MACH_MINI2440=y
-CONFIG_MINI2440_VIDEO_N35=y
-CONFIG_S3C_NAND_BOOT=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PROMPT="mini2440:"
-CONFIG_GLOB=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/friendlyarm-mini2440/env"
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_GLOBAL=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_DM9K=y
-# CONFIG_SPI is not set
-CONFIG_USB_HOST=y
-CONFIG_USB_OHCI=y
-CONFIG_MCI=y
-CONFIG_MCI_S3C=y
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/friendlyarm_mini6410_defconfig b/arch/arm/configs/friendlyarm_mini6410_defconfig
deleted file mode 100644
index 8beee6f194..0000000000
--- a/arch/arm/configs/friendlyarm_mini6410_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-CONFIG_ARCH_S3C64xx=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PROMPT="mini6410:"
-CONFIG_GLOB=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_GPIO=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_DM9K=y
-# CONFIG_SPI is not set
-CONFIG_ZLIB=y
-CONFIG_BZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/friendlyarm_tiny210_defconfig b/arch/arm/configs/friendlyarm_tiny210_defconfig
deleted file mode 100644
index 1d1647931f..0000000000
--- a/arch/arm/configs/friendlyarm_tiny210_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARCH_S5PCxx=y
-CONFIG_S3C_PLL_INIT=y
-CONFIG_CMD_LED=y
-CONFIG_CMD_LED_TRIGGER=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_TRIGGERS=y
diff --git a/arch/arm/configs/friendlyarm_tiny6410_defconfig b/arch/arm/configs/friendlyarm_tiny6410_defconfig
deleted file mode 100644
index 12dbea1317..0000000000
--- a/arch/arm/configs/friendlyarm_tiny6410_defconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-CONFIG_ARCH_S3C64xx=y
-CONFIG_MACH_TINY6410=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PROMPT="tiny6410:"
-CONFIG_GLOB=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_GPIO=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_DM9K=y
-# CONFIG_SPI is not set
-CONFIG_ZLIB=y
-CONFIG_BZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
deleted file mode 100644
index aa2ae67e2d..0000000000
--- a/arch/arm/mach-samsung/Kconfig
+++ /dev/null
@@ -1,178 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config ARCH_SAMSUNG
-	bool
-
-if ARCH_SAMSUNG
-
-config ARCH_TEXT_BASE
-	hex
-	default 0x31fc0000 if MACH_MINI2440
-	default 0x57fc0000 if MACH_MINI6410
-	default 0x57fc0000 if MACH_TINY6410
-	default 0x31fc0000 if MACH_A9M2440
-	default 0x31fc0000 if MACH_A9M2410
-	default 0x23e00000 if MACH_TINY210
-
-config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
-	hex
-	default 0x1ff0 if ARCH_S5PCxx
-# TODO
-	default 0x2000 if ARCH_S3C64xx
-
-if ARCH_S3C24xx
-
-config CPU_S3C2410
-	bool
-
-config CPU_S3C2440
-	bool
-
-choice
-	prompt "S3C24xx Board Type"
-
-config MACH_A9M2410
-	bool "Digi A9M2410"
-	select CPU_S3C2410
-	select S3C_PLL_INIT
-	select S3C_SDRAM_INIT
-	help
-	  Say Y here if you are using Digi's Connect Core 9M equipped
-	  with a Samsung S3C2410 Processor
-
-config MACH_A9M2440
-	bool "Digi A9M2440"
-	select CPU_S3C2440
-	select S3C_PLL_INIT
-	help
-	  Say Y here if you are using Digi's Connect Core 9M equipped
-	  with a Samsung S3C2440 Processor
-
-config MACH_MINI2440
-	bool "Mini 2440"
-	select CPU_S3C2440
-	select S3C_PLL_INIT
-	select S3C_SDRAM_INIT
-	select HAS_DM9000
-	help
-	  Say Y here if you are using Mini 2440 dev board equipped
-	  with a Samsung S3C2440 Processor
-
-endchoice
-
-menu "Board specific settings"
-
-choice
-	prompt "A9M2440 baseboard"
-	depends on MACH_A9M2440
-
-config MACH_A9M2410DEV
-	bool
-	prompt "A9M2410dev"
-	select HAS_CS8900
-	help
-	  Digi's evaluation board.
-
-endchoice
-
-source "arch/arm/boards/friendlyarm-mini2440/Kconfig"
-
-endmenu
-
-endif
-
-if ARCH_S3C64xx
-
-config CPU_S3C6410
-	bool
-
-choice
-	prompt "S3C64xx Board Type"
-
-config MACH_MINI6410
-	bool "Mini 6410"
-	select CPU_S3C6410
-	select HAS_DM9000
-	help
-	  Say Y here if you are using FriendlyARM Mini6410 board equipped
-	  with a Samsung S3C6410 Processor
-
-config MACH_TINY6410
-	bool "Tiny 6410"
-	select CPU_S3C6410
-	help
-	  Say Y here if you are using FriendlyARM Tiny6410 CPU card equipped
-	  with a Samsung S3C6410 Processor
-
-endchoice
-
-menu "Board specific settings"
-
-source "arch/arm/boards/friendlyarm-tiny6410/Kconfig"
-
-endmenu
-
-endif
-
-if ARCH_S5PCxx
-
-config CPU_S5PC110
-	bool
-
-config CPU_S5PV210
-	bool
-
-choice
-	prompt "S5PCxx board type"
-
-config MACH_TINY210
-	bool "Tiny 210"
-	select CPU_S5PV210
-	select S3C_SDRAM_INIT
-
-endchoice
-
-endif
-
-menu "S3C Features"
-
-config S3C_LOWLEVEL_INIT
-	bool
-
-config S3C_PLL_INIT
-	bool
-	prompt "Reconfigure PLL"
-	select S3C_LOWLEVEL_INIT
-	help
-	  This adds generic code to reconfigure the internal PLL very early
-	  after reset.
-
-config S3C_SDRAM_INIT
-	bool
-	prompt "Initialize SDRAM"
-	select S3C_LOWLEVEL_INIT
-	help
-	  This adds generic code to configure the SDRAM controller after reset.
-	  The initialisation will be skipped if the code is already running
-	  from SDRAM.
-
-config S3C_NAND_BOOT
-	bool
-	prompt "Booting from NAND"
-	depends on ARCH_S3C24xx
-	select MTD
-	select NAND
-	select NAND_S3C24XX
-	help
-	  Add generic support to boot from NAND flash. Image loading will be
-	  skipped if the code is running from NOR or already from SDRAM.
-
-config BAREBOX_UPDATE_NAND_S3C24XX
-	bool
-	depends on BAREBOX_UPDATE
-	depends on S3C_NAND_BOOT
-	default y
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
deleted file mode 100644
index 8a893a076f..0000000000
--- a/arch/arm/mach-samsung/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-obj-y += s3c-timer.o generic.o
-obj-$(CONFIG_RESET_SOURCE) += reset_source.o
-obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
-obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
-pbl-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
-pbl-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
-obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
-obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o mem-s3c64xx.o
-obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
-pbl-$(CONFIG_ARCH_S5PCxx) += mem-s5pcxx.o
-obj-$(CONFIG_BAREBOX_UPDATE_NAND_S3C24XX) += bbu-nand-s3c24x0.o
-obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/bbu-nand-s3c24x0.c b/arch/arm/mach-samsung/bbu-nand-s3c24x0.c
deleted file mode 100644
index 0d25abfeb7..0000000000
--- a/arch/arm/mach-samsung/bbu-nand-s3c24x0.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2014 Michael Olbrich, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation.
- *
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <bbu.h>
-#include <fs.h>
-#include <fcntl.h>
-
-static int nand_update(struct bbu_handler *handler, struct bbu_data *data)
-{
-	int fd, ret;
-
-	if (file_detect_type(data->image, data->len) != filetype_arm_barebox &&
-			!bbu_force(data, "Not an ARM barebox image"))
-		return -EINVAL;
-
-	ret = bbu_confirm(data);
-	if (ret)
-		return ret;
-
-	fd = open(data->devicefile, O_WRONLY);
-	if (fd < 0)
-		return fd;
-
-	debug("%s: eraseing %s from 0 to 0x%08x\n", __func__,
-			data->devicefile, data->len);
-	ret = erase(fd, data->len, 0);
-	if (ret) {
-		printf("erasing %s failed with %s\n", data->devicefile,
-				strerror(-ret));
-		goto err_close;
-	}
-
-	ret = write(fd, data->image, data->len);
-	if (ret < 0) {
-		printf("writing update to %s failed with %s\n", data->devicefile,
-				strerror(-ret));
-		goto err_close;
-	}
-
-	ret = 0;
-
-err_close:
-	close(fd);
-
-	return ret;
-}
-
-/*
- * Register a s3c24x0 update handler for NAND
- */
-int s3c24x0_bbu_nand_register_handler(void)
-{
-	struct bbu_handler *handler;
-	int ret;
-
-	handler = xzalloc(sizeof(*handler));
-	handler->devicefile = "/dev/nand0.barebox";
-	handler->name = "nand";
-	handler->handler = nand_update;
-	handler->flags = BBU_HANDLER_FLAG_DEFAULT;
-
-	ret = bbu_register_handler(handler);
-	if (ret)
-		free(handler);
-
-	return ret;
-}
diff --git a/arch/arm/mach-samsung/clocks-s3c24xx.c b/arch/arm/mach-samsung/clocks-s3c24xx.c
deleted file mode 100644
index a2dd869672..0000000000
--- a/arch/arm/mach-samsung/clocks-s3c24xx.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-clocks.h>
-#include <mach/s3c-busctl.h>
-
-/**
- * Calculate the current M-PLL clock.
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_mpllclk(void)
-{
-	uint32_t m, p, s, reg_val;
-
-	reg_val = readl(S3C_MPLLCON);
-	m = ((reg_val & 0xFF000) >> 12) + 8;
-	p = ((reg_val & 0x003F0) >> 4) + 2;
-	s = reg_val & 0x3;
-#ifdef CONFIG_CPU_S3C2410
-	return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-#endif
-#ifdef CONFIG_CPU_S3C2440
-	return 2 * m * (S3C24XX_CLOCK_REFERENCE / (p << s));
-#endif
-}
-
-/**
- * Calculate the current U-PLL clock
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_upllclk(void)
-{
-	uint32_t m, p, s, reg_val;
-
-	reg_val = readl(S3C_UPLLCON);
-	m = ((reg_val & 0xFF000) >> 12) + 8;
-	p = ((reg_val & 0x003F0) >> 4) + 2;
-	s = reg_val & 0x3;
-
-	return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-}
-
-/**
- * Calculate the FCLK frequency used for the ARM CPU core
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_fclk(void)
-{
-	return s3c_get_mpllclk();
-}
-
-/**
- * Calculate the HCLK frequency used for the AHB bus (CPU to main peripheral)
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_hclk(void)
-{
-	uint32_t f_clk;
-
-	f_clk = s3c_get_fclk();
-#ifdef CONFIG_CPU_S3C2410
-	if (readl(S3C_CLKDIVN) & 0x02)
-		return f_clk >> 1;
-#endif
-#ifdef CONFIG_CPU_S3C2440
-	switch(readl(S3C_CLKDIVN) & 0x06) {
-	case 2:
-		return f_clk >> 1;
-	case 4:
-		return f_clk >> 2;	/* TODO consider CAMDIVN */
-	case 6:
-		return f_clk / 3;	/* TODO consider CAMDIVN */
-	}
-#endif
-	return f_clk;
-}
-
-/**
- * Calculate the PCLK frequency used for the slower peripherals
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_pclk(void)
-{
-	uint32_t p_clk;
-
-	p_clk = s3c_get_hclk();
-	if (readl(S3C_CLKDIVN) & 0x01)
-		return p_clk >> 1;
-	return p_clk;
-}
-
-/**
- * Return correct UART frequency based on the UCON register
- */
-unsigned s3c_get_uart_clk(unsigned src)
-{
-	switch (src & 3) {
-	case 0:
-	case 2:
-		return s3c_get_pclk();
-	case 1:
-		return 0; /* TODO UEXTCLK */
-	case 3:
-		return 0; /* TODO FCLK/n */
-	}
-	return 0; /* not reached, to make compiler happy */
-}
-
-/**
- * Show the user the current clock settings
- */
-static int s3c24xx_dump_clocks(void)
-{
-	printf("refclk:  %7d kHz\n", S3C24XX_CLOCK_REFERENCE / 1000);
-	printf("mpll:    %7d kHz\n", s3c_get_mpllclk() / 1000);
-	printf("upll:    %7d kHz\n", s3c_get_upllclk() / 1000);
-	printf("fclk:    %7d kHz\n", s3c_get_fclk() / 1000);
-	printf("hclk:    %7d kHz\n", s3c_get_hclk() / 1000);
-	printf("pclk:    %7d kHz\n", s3c_get_pclk() / 1000);
-	printf("SDRAM1:   CL%d@%dMHz\n", ((readl(S3C_BANKCON6) & 0xc) >> 2) + 2,
-						s3c_get_hclk() / 1000000);
-	if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
-		printf("SDRAM2:   CL%d@%dMHz\n",
-			((readl(S3C_BANKCON7) & 0xc) >> 2) + 2,
-			s3c_get_hclk() / 1000000);
-	return 0;
-}
-
-late_initcall(s3c24xx_dump_clocks);
diff --git a/arch/arm/mach-samsung/clocks-s3c64xx.c b/arch/arm/mach-samsung/clocks-s3c64xx.c
deleted file mode 100644
index 2229ed0529..0000000000
--- a/arch/arm/mach-samsung/clocks-s3c64xx.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <linux/math64.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-clocks.h>
-
-/*
- * The main clock tree:
- *
- * ref_in
- *    |
- *    v
- *    o-----------\
- *    |            MUX -o------------\
- *    |           / ^   |             MUX --- DIV_APLL ------- ARMCLK -> CPU core
- *    o--- APLL --  |   |            / |
- *    |             |   o--/2 -------  |
- *    |       APLL_SEL  |              |<-MISC_CON_SYN667
- *    |                 \              |
- *    o-----------\      MUX-o-------\ |
- *    |            MUX--/ ^  |        MUX --- DIV -o--------- HCLKx2 -> SDRAM (max. 266 MHz)
- *    |           / ^     |  |       /             |
- *    o---- MPLL--  |     |  o--/5 --              o-- DIV -- HCLK -> AXI / AHB (max. 133 MHz)
- *    |             |     |                        |
- *    |       MPLL_SEL  OTHERS_CLK_SELECT          o-- DIV -- PCLK -> APB (max. 66 MHz)
- *    |
- *    o-----------\
- *    |            MUX---- to various hardware
- *    |           / ^
- *    o---- EPLL--  EPLL_SEL
- *
- */
-
-static unsigned s3c_get_apllclk(void)
-{
-	uint32_t m, p, s, reg_val;
-
-	if (!(readl(S3C_CLK_SRC) & S3C_CLK_SRC_FOUTAPLL))
-		return S3C64XX_CLOCK_REFERENCE;
-
-	reg_val = readl(S3C_APLLCON);
-	if (!(reg_val & S3C_APLLCON_ENABLE))
-		return 0;
-	m = S3C_APLLCON_GET_MDIV(reg_val);
-	p = S3C_APLLCON_GET_PDIV(reg_val);
-	s = S3C_APLLCON_GET_SDIV(reg_val);
-
-	return (S3C64XX_CLOCK_REFERENCE * m) / (p << s);
-}
-
-uint32_t s3c_get_mpllclk(void)
-{
-	uint32_t m, p, s, reg_val;
-
-	if (!(readl(S3C_CLK_SRC) & S3C_CLK_SRC_FOUTMPLL))
-		return S3C64XX_CLOCK_REFERENCE;
-
-	reg_val = readl(S3C_MPLLCON);
-	if (!(reg_val & S3C_MPLLCON_ENABLE))
-		return 0;
-
-	m = S3C_MPLLCON_GET_MDIV(reg_val);
-	p = S3C_MPLLCON_GET_PDIV(reg_val);
-	s = S3C_MPLLCON_GET_SDIV(reg_val);
-
-	return (S3C64XX_CLOCK_REFERENCE * m) / (p << s);
-}
-
-unsigned s3c_get_epllclk(void)
-{
-	u32 m, p, s, k, reg0_val, reg1_val;
-	u64 tmp;
-
-	if (!(readl(S3C_CLK_SRC) & S3C_CLK_SRC_FOUTEPLL))
-		return S3C64XX_CLOCK_REFERENCE;
-
-	reg0_val = readl(S3C_EPLLCON0);
-	if (!(reg0_val & S3C_EPLLCON0_ENABLE))
-		return 0;	/* PLL is disabled */
-
-	reg1_val = readl(S3C_EPLLCON1);
-	m = S3C_EPLLCON0_GET_MDIV(reg0_val);
-	p = S3C_EPLLCON0_GET_PDIV(reg0_val);
-	s = S3C_EPLLCON0_GET_SDIV(reg0_val);
-	k = S3C_EPLLCON1_GET_KDIV(reg1_val);
-
-	tmp = S3C64XX_CLOCK_REFERENCE;
-	tmp *= (m << 16) + k;
-	do_div(tmp, (p << s));
-
-	return (unsigned)(tmp >> 16);
-}
-
-unsigned s3c_set_epllclk(unsigned m, unsigned p, unsigned s, unsigned k)
-{
-	u32 con0, con1, src = readl(S3C_CLK_SRC) & ~S3C_CLK_SRC_FOUTEPLL;
-
-	/* do not use the EPLL clock when it is in transit to the new frequency */
-	writel(src, S3C_CLK_SRC);
-
-	con0 = S3C_EPLLCON0_SET_MDIV(m) | S3C_EPLLCON0_SET_PDIV(p) |
-				S3C_EPLLCON0_SET_SDIV(s) | S3C_EPLLCON0_ENABLE;
-	con1 = S3C_EPLLCON1_SET_KDIV(k);
-
-	/*
-	 * After changing the multiplication value 'm' the PLL output will
-	 * be masked for the time set in the EPLL_LOCK register until it
-	 * settles to the new frequency. EPLL_LOCK contains a value for a
-	 * simple counter which counts the external reference clock.
-	 */
-	writel(con0, S3C_EPLLCON0);
-	writel(con1, S3C_EPLLCON1);
-
-	udelay((1000000000 / S3C64XX_CLOCK_REFERENCE)
-		* (S3C_EPLL_LOCK_PLL_LOCKTIME(readl(S3C_EPLL_LOCK)) + 1) / 1000);
-
-	/* enable the EPLL's clock output to the system */
-	writel(src | S3C_CLK_SRC_FOUTEPLL, S3C_CLK_SRC);
-
-	return s3c_get_epllclk();
-}
-
-uint32_t s3c_get_fclk(void)
-{
-	unsigned clk;
-
-	clk = s3c_get_apllclk();
-	if (readl(S3C_MISC_CON) & S3C_MISC_CON_SYN667)
-		clk /= 2;
-
-	return clk / (S3C_CLK_DIV0_GET_ADIV(readl(S3C_CLK_DIV0)) + 1);
-}
-
-static unsigned s3c_get_hclk_in(void)
-{
-	unsigned clk;
-
-	if (readl(S3C_OTHERS) & S3C_OTHERS_CLK_SELECT)
-		clk = s3c_get_apllclk();
-	else
-		clk = s3c_get_mpllclk();
-
-	if (readl(S3C_MISC_CON) & S3C_MISC_CON_SYN667)
-		clk /= 5;
-
-	return clk;
-}
-
-static unsigned s3c_get_hclkx2(void)
-{
-	return s3c_get_hclk_in() /
-			(S3C_CLK_DIV0_GET_HCLK2(readl(S3C_CLK_DIV0)) + 1);
-}
-
-uint32_t s3c_get_hclk(void)
-{
-	return s3c_get_hclkx2() /
-			(S3C_CLK_DIV0_GET_HCLK(readl(S3C_CLK_DIV0)) + 1);
-}
-
-uint32_t s3c_get_pclk(void)
-{
-	return s3c_get_hclkx2() /
-			(S3C_CLK_DIV0_GET_PCLK(readl(S3C_CLK_DIV0)) + 1);
-}
-
-static void s3c_init_mpll_dout(void)
-{
-	unsigned reg;
-
-	/* keep it at the same frequency as HCLKx2 */
-	reg = readl(S3C_CLK_DIV0) | S3C_CLK_DIV0_SET_MPLL_DIV(1); /* e.g. / 2 */
-	writel(reg, S3C_CLK_DIV0);
-}
-
-/* configure and enable UCLK1 */
-static int s3c_init_uart_clock(void)
-{
-	unsigned reg;
-
-	s3c_init_mpll_dout();	/* to have a reliable clock source */
-
-	/* source the UART clock from the MPLL, currently *not* from EPLL */
-	reg = readl(S3C_CLK_SRC) | S3C_CLK_SRC_UARTMPLL;
-	writel(reg, S3C_CLK_SRC);
-
-	/* keep UART clock at the same frequency than the PCLK */
-	reg = readl(S3C_CLK_DIV2) & ~S3C_CLK_DIV2_UART_MASK;
-	reg |= S3C_CLK_DIV2_SET_UART(0x3);	/* / 4 */
-	writel(reg, S3C_CLK_DIV2);
-
-	/* ensure this very special clock is running */
-	reg = readl(S3C_SCLK_GATE) | S3C_SCLK_GATE_UART;
-	writel(reg, S3C_SCLK_GATE);
-
-	return 0;
-}
-core_initcall(s3c_init_uart_clock);
-
-/*                                         UART source selection
- * The UART related clock path:                     |
- *                                                  v
- * PCLK --------------------------------------o-----0-\
- * ???? -------------------------------UCLK0--|-----1--\MUX----- UART
- * MPLL -----DIV0------\                      +-----2--/
- *                     MUX---DIV2------UCLK1--------3-/
- * EPLL ---------------/
- *                      ^SRC_UARTMPLL
- */
-unsigned s3c_get_uart_clk(unsigned source)
-{
-	u32 reg;
-	unsigned clk, pdiv, uartpdiv;
-
-	switch (source) {
-	default: /* PCLK */
-		clk = s3c_get_pclk();
-		pdiv = uartpdiv = 1;
-		break;
-	case 1: /* UCLK0 */
-		clk = 0;
-		pdiv = uartpdiv = 1;	/* TODO */
-		break;
-	case 3: /* UCLK1 */
-		reg = readl(S3C_CLK_SRC);
-		if (reg & S3C_CLK_SRC_UARTMPLL) {
-			clk = s3c_get_mpllclk();
-			pdiv = S3C_CLK_DIV0_GET_MPLL_DIV(readl(S3C_CLK_DIV0)) + 1;
-		} else {
-			clk = s3c_get_epllclk();
-			pdiv = 1;
-		}
-		uartpdiv = S3C_CLK_DIV2_GET_UART(readl(S3C_CLK_DIV2)) + 1;
-		break;
-	}
-
-	return clk / pdiv / uartpdiv;
-}
-
-/*
- * The MMC related clock path:
- *
- *              MMCx_SEL
- *                 |
- *                 v
- * EPLLout --------0-\
- * MPLLout --DIV0--1--\-------SCLK_MMCx----DIV_MMCx------>HSMMCx
- * EPLLin  --------2--/        on/off      / 1..16
- * 27 MHz  --------3-/
- *
- * The datasheet is not very precise here, so the schematic shown above was
- * made by checking various bits in the SYSCON.
- */
-unsigned s3c_get_hsmmc_clk(int id)
-{
-	u32 sel, div, sclk = readl(S3C_SCLK_GATE);
-	unsigned bclk;
-
-	if (!(sclk & S3C_SCLK_GATE_MMC(id)))
-		return 0; /* disabled */
-
-	sel = S3C_CLK_SRC_GET_MMC_SEL(id, readl(S3C_CLK_SRC));
-	switch (sel) {
-	case 0:
-		bclk = s3c_get_epllclk();
-		break;
-	case 1:
-		bclk = s3c_get_mpllclk();
-		bclk >>= S3C_CLK_DIV0_GET_MPLL_DIV(readl(S3C_CLK_DIV0));
-		break;
-	case 2:
-		bclk = S3C64XX_CLOCK_REFERENCE;
-		break;
-	case 3:
-		bclk = 27000000;
-		break;
-	}
-
-	div = S3C_CLK_DIV0_GET_MMC(id, readl(S3C_CLK_DIV0)) + 1;
-
-	return bclk / div;
-}
-
-void s3c_set_hsmmc_clk(int id, int src, unsigned div)
-{
-	u32 reg;
-
-	if (!div)
-		div = 1;
-
-	writel(readl(S3C_SCLK_GATE) & ~S3C_SCLK_GATE_MMC(id), S3C_SCLK_GATE);
-
-	/* select the new clock source */
-	reg = readl(S3C_CLK_SRC) & ~S3C_CLK_SRC_SET_MMC_SEL(id, ~0);
-	reg |= S3C_CLK_SRC_SET_MMC_SEL(id, src);
-	writel(reg, S3C_CLK_SRC);
-
-	/* select the new pre-divider */
-	reg = readl(S3C_CLK_DIV0) & ~ S3C_CLK_DIV0_SET_MMC(id, ~0);
-	reg |= S3C_CLK_DIV0_SET_MMC(id, div - 1);
-	writel(reg, S3C_CLK_DIV0);
-
-	/* calling this function implies enabling of the clock */
-	writel(readl(S3C_SCLK_GATE) | S3C_SCLK_GATE_MMC(id), S3C_SCLK_GATE);
-}
-
-static int s3c64xx_dump_clocks(void)
-{
-	printf("refclk:  %7d kHz\n", S3C64XX_CLOCK_REFERENCE / 1000);
-	printf("apll:    %7d kHz\n", s3c_get_apllclk() / 1000);
-	printf("mpll:    %7d kHz\n", s3c_get_mpllclk() / 1000);
-	printf("epll:    %7d kHz\n", s3c_get_epllclk() / 1000);
-	printf("CPU:     %7d kHz\n", s3c_get_fclk() / 1000);
-	printf("hclkx2:  %7d kHz\n", s3c_get_hclkx2() / 1000);
-	printf("hclk:    %7d kHz\n", s3c_get_hclk() / 1000);
-	printf("pclk:    %7d kHz\n", s3c_get_pclk() / 1000);
-	return 0;
-}
-
-late_initcall(s3c64xx_dump_clocks);
diff --git a/arch/arm/mach-samsung/clocks-s5pcxx.c b/arch/arm/mach-samsung/clocks-s5pcxx.c
deleted file mode 100644
index 4a1574bd89..0000000000
--- a/arch/arm/mach-samsung/clocks-s5pcxx.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- * Copyright (C) 2012 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-clocks.h>
-
-static inline uint32_t clkdiv(uint32_t clk, unsigned bit, unsigned mask)
-{
-	uint32_t ratio = (readl(S5P_CLK_DIV0) >> bit) & mask;
-	return clk / (ratio + 1);
-}
-
-uint32_t s3c_get_mpllclk(void)
-{
-	uint32_t m, p, s;
-	uint32_t reg = readl(S5P_xPLL_CON + S5P_MPLL);
-	m = (reg >> 16) & 0x3ff;
-	p = (reg >> 8) & 0x3f;
-	s = (reg >> 0) & 0x7;
-	return m * ((S5PCXX_CLOCK_REFERENCE) / (p << s));
-}
-
-static uint32_t s3c_get_apllclk(void)
-{
-	uint32_t m, p, s;
-	uint32_t reg = readl(S5P_xPLL_CON + S5P_APLL);
-	m = (reg >> 16) & 0x3ff;
-	p = (reg >> 8) & 0x3f;
-	s = (reg >> 0) & 0x7;
-	s -= 1;
-	return m * ((S5PCXX_CLOCK_REFERENCE) / (p << s));
-}
-
-static uint32_t s5p_get_a2mclk(void)
-{
-	return clkdiv(s3c_get_apllclk(), 4, 0x7);
-}
-
-static uint32_t s5p_get_moutpsysclk(void)
-{
-	if (readl(S5P_CLK_SRC0) & (1 << 24)) /* MUX_PSYS */
-		return s5p_get_a2mclk();
-        else
-		return s3c_get_mpllclk();
-}
-
-uint32_t s3c_get_hclk(void)
-{
-	return clkdiv(s5p_get_moutpsysclk(), 24, 0xf);
-}
-
-uint32_t s3c_get_pclk(void)
-{
-	return clkdiv(s3c_get_hclk(), 28, 0x7);
-}
-
-/* we are using the internal 'uclk1' as the UART source */
-static unsigned s3c_get_uart_clk_uclk1(void)
-{
-	unsigned clk = s3c_get_mpllclk();	/* TODO check for EPLL */
-	unsigned uartpdiv = ((readl(S5P_CLK_DIV4) >> 16) & 0x3) + 1; /* TODO this is UART0 only */
-	return clk / uartpdiv;
-}
-
-unsigned s3c_get_uart_clk(unsigned src) {
-	return (src & 1) ? s3c_get_uart_clk_uclk1() : s3c_get_pclk();
-}
-
-static int s5pcxx_dump_clocks(void)
-{
-	printf("refclk:  %7d kHz\n", S5PCXX_CLOCK_REFERENCE / 1000);
-	printf("apll:    %7d kHz\n", s3c_get_apllclk() / 1000);
-	printf("mpll:    %7d kHz\n", s3c_get_mpllclk() / 1000);
-/*	printf("CPU:     %7d kHz\n", s3c_get_cpuclk() / 1000); */
-	printf("hclk:    %7d kHz\n", s3c_get_hclk() / 1000);
-	printf("pclk:    %7d kHz\n", s3c_get_pclk() / 1000);
-	return 0;
-}
-
-late_initcall(s5pcxx_dump_clocks);
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
deleted file mode 100644
index ed3d30d995..0000000000
--- a/arch/arm/mach-samsung/generic.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-/**
- * @file
- * @brief Basic clock, sdram and timer handling for S3C24xx CPUs
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <restart.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-
-#define S3C_WTCON (S3C_WATCHDOG_BASE)
-#define S3C_WTDAT (S3C_WATCHDOG_BASE + 0x04)
-#define S3C_WTCNT (S3C_WATCHDOG_BASE + 0x08)
-
-static void __noreturn samsung_restart_soc(struct restart_handler *rst)
-{
-	/* Disable watchdog */
-	writew(0x0000, S3C_WTCON);
-
-	/* Initialize watchdog timer count register */
-	writew(0x0001, S3C_WTCNT);
-
-	/* Enable watchdog timer; assert reset at timer timeout */
-	writew(0x0021, S3C_WTCON);
-
-	/* loop forever and wait for reset to happen */
-	hang();
-}
-
-static int restart_register_feature(void)
-{
-	restart_handler_register_fn("soc-wdt", samsung_restart_soc);
-
-	return 0;
-}
-coredevice_initcall(restart_register_feature);
diff --git a/arch/arm/mach-samsung/gpio-s3c24x0.c b/arch/arm/mach-samsung/gpio-s3c24x0.c
deleted file mode 100644
index 58ca284eab..0000000000
--- a/arch/arm/mach-samsung/gpio-s3c24x0.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <errno.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <gpio.h>
-#include <mach/s3c24xx-gpio.h>
-#include <mach/iomux.h>
-
-static const unsigned char group_offset[] =
-{
-	0x00,	/* GPA */
-	0x10,	/* GPB */
-	0x20,	/* GPC */
-	0x30,	/* GPD */
-	0x40,	/* GPE */
-	0x50,	/* GPF */
-	0x60,	/* GPG */
-	0x70,	/* GPH */
-#ifdef CONFIG_CPU_S3C2440
-	0xd0,	/* GPJ */
-#endif
-};
-
-void gpio_set_value(unsigned gpio, int value)
-{
-	unsigned group = gpio >> 5;
-	unsigned bit = gpio % 32;
-	unsigned offset;
-	uint32_t reg;
-
-	offset = group_offset[group];
-
-	reg = readl(S3C_GPADAT + offset);
-	reg &= ~(1 << bit);
-	reg |= (!!value) << bit;
-	writel(reg, S3C_GPADAT + offset);
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	unsigned group = gpio >> 5;
-	unsigned bit = gpio % 32;
-	unsigned offset;
-	uint32_t reg;
-
-	offset = group_offset[group];
-
-	reg = readl(S3C_GPACON + offset);
-	reg &= ~(0x3 << (bit << 1));
-	writel(reg, S3C_GPACON + offset);
-
-	return 0;
-}
-
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-	unsigned group = gpio >> 5;
-	unsigned bit = gpio % 32;
-	unsigned offset;
-	uint32_t reg;
-
-	offset = group_offset[group];
-
-	/* value */
-	gpio_set_value(gpio,value);
-	/* direction */
-	if (group == 0) {	/* GPA is special */
-		reg = readl(S3C_GPACON);
-		reg &= ~(1 << bit);
-		writel(reg, S3C_GPACON);
-	} else {
-		reg = readl(S3C_GPACON + offset);
-		reg &= ~(0x3 << (bit << 1));
-		reg |= 0x1 << (bit << 1);
-		writel(reg, S3C_GPACON + offset);
-	}
-
-	return 0;
-}
-
-int gpio_get_value(unsigned gpio)
-{
-	unsigned group = gpio >> 5;
-	unsigned bit = gpio % 32;
-	unsigned offset;
-	uint32_t reg;
-
-	if (group == 0)	/* GPA is special: no input mode available */
-		return -ENODEV;
-
-	offset = group_offset[group];
-
-	/* value */
-	reg = readl(S3C_GPADAT + offset);
-
-	return !!(reg & (1 << bit));
-}
-
-void s3c_gpio_mode(unsigned gpio_mode)
-{
-	unsigned group, func, bit, offset, gpio;
-	uint32_t reg;
-
-	group = GET_GROUP(gpio_mode);
-	func = GET_FUNC(gpio_mode);
-	bit = GET_BIT(gpio_mode);
-	gpio = GET_GPIO_NO(gpio_mode);
-
-	if (group == 0) {
-		/* GPA is special */
-		switch (func) {
-		case 0:		/* GPIO input */
-			pr_debug("Cannot set GPA pin to GPIO input\n");
-			break;
-		case 1:		/* GPIO output */
-			gpio_direction_output(bit, GET_GPIOVAL(gpio_mode));
-			break;
-		default:
-			reg = readl(S3C_GPACON);
-			reg |= 1 << bit;
-			writel(reg, S3C_GPACON);
-			break;
-		}
-		return;
-	}
-
-	offset = group_offset[group];
-
-	if (PU_PRESENT(gpio_mode)) {
-		reg = readl(S3C_GPACON + offset + 8);
-		if (GET_PU(gpio_mode))
-			reg |= (1 << bit);	/* set means _disabled_ */
-		else
-			reg &= ~(1 << bit);
-		writel(reg, S3C_GPACON + offset + 8);
-	}
-
-	switch (func) {
-	case 0: /* input */
-		gpio_direction_input(gpio);
-		break;
-	case 1:	/* output */
-		gpio_direction_output(gpio, GET_GPIOVAL(gpio_mode));
-		break;
-	case 2: /* function one */
-	case 3: /* function two */
-		reg = readl(S3C_GPACON + offset);
-		reg &= ~(0x3 << (bit << 1));
-		reg |= func << (bit << 1);
-		writel(reg, S3C_GPACON + offset);
-		break;
-	}
-}
diff --git a/arch/arm/mach-samsung/gpio-s3c64xx.c b/arch/arm/mach-samsung/gpio-s3c64xx.c
deleted file mode 100644
index d70a8716c9..0000000000
--- a/arch/arm/mach-samsung/gpio-s3c64xx.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This code bases partially on code from the Linux kernel:
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *	http://armlinux.simtec.co.uk/
- *	Ben Dooks <ben at simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <errno.h>
-#include <io.h>
-#include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/s3c-iomap.h>
-
-#define S3C_GPACON (S3C_GPIO_BASE)
-#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
-#define S3C_GPAPUD (S3C_GPIO_BASE + 0x08)
-
-static const unsigned short group_offset[] = {
-	0x000,	/* GPA */ /* 8 pins, 4 bit each */
-	0x020,	/* GPB */ /* 7 pins, 4 bit each */
-	0x040,	/* GPC */ /* 8 pins, 4 bit each */
-	0x060,	/* GPD */ /* 5 pins, 4 bit each */
-	0x080,	/* GPE */ /* 5 pins, 4 bit each */
-	0x0a0,	/* GPF */ /* 16 pins, 2 bit each */
-	0x0c0,	/* GPG */ /* 7 pins, 4 bit each */
-	0x0e0,	/* GPH */ /* two registers, 8 + 2 pins, 4 bit each */
-	0x100,	/* GPI */ /* 16 pins, 2 bit each */
-	0x120,	/* GPJ */ /* 12 pins, 2 bit each */
-	0x800,	/* GPK */ /* two registers, 8 + 8 pins, 4 bit each */
-	0x810,	/* GPL */ /* two registers, 8 + 8 pins, 4 bit each */
-	0x820,	/* GPM */ /* 6 pins, 4 bit each */
-	0x830,	/* GPN */ /* 16 pins, 2 bit each */
-	0x140,	/* GPO */ /* 16 pins, 2 bit each */
-	0x160,	/* GPP */ /* 15 pins, 2 bit each */
-	0x180,	/* GPQ */ /* 9 pins, 2 bit each */
-};
-
-void gpio_set_value(unsigned gpio, int value)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset;
-	uint32_t reg;
-
-	offset = group_offset[group];
-
-	switch (group) {
-	case 7:		/* GPH */
-	case 10:	/* GPK */
-	case 11:	/* GPL */
-		offset += 4;
-		break;
-	}
-
-	reg = readl(S3C_GPADAT + offset);
-	reg &= ~(1 << bit);
-	reg |= (!!value) << bit;
-	writel(reg, S3C_GPADAT + offset);
-}
-
-int gpio_get_value(unsigned gpio)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset;
-	uint32_t reg;
-
-	offset = group_offset[group];
-
-	switch (group) {
-	case 7:		/* GPH */
-	case 10:	/* GPK */
-	case 11:	/* GPL */
-		offset += 4;
-		break;
-	}
-
-	/* value */
-	reg = readl(S3C_GPADAT + offset);
-
-	return !!(reg & (1 << bit));
-}
-
-static void gpio_direction_input_4b(unsigned offset, unsigned bit)
-{
-	uint32_t reg;
-
-	if (bit > 31) {
-		offset += 4;
-		bit -= 32;
-	}
-
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	writel(reg, S3C_GPACON + offset); /* b0000 means 'GPIO input' */
-}
-
-static void gpio_direction_input_2b(unsigned offset, unsigned bit)
-{
-	uint32_t reg;
-
-	reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
-	writel(reg, S3C_GPACON + offset); /* b00 means 'GPIO input' */
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset;
-
-	offset = group_offset[group];
-
-	switch (group) {
-	case 5:		/* GPF */
-	case 8:		/* GPI */
-	case 9:		/* GPJ */
-	case 13:	/* GPN */
-	case 14:	/* GPO */
-	case 15:	/* GPP */
-	case 16:	/* GPQ */
-		gpio_direction_input_2b(offset, bit << 1);
-		break;
-	default:
-		gpio_direction_input_4b(offset, bit << 2);
-	}
-
-	return 0;
-}
-
-static void gpio_direction_output_4b(unsigned offset, unsigned bit)
-{
-	uint32_t reg;
-
-	if (bit > 31) {
-		offset += 4;
-		bit -= 32;
-	}
-
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	reg |= 0x1 << bit;
-	writel(reg, S3C_GPACON + offset); /* b0001 means 'GPIO output' */
-}
-
-static void gpio_direction_output_2b(unsigned offset, unsigned bit)
-{
-	uint32_t reg;
-
-	/* direction */
-	reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
-	reg |= 0x1 << bit;
-	writel(reg, S3C_GPACON + offset);
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset;
-
-	gpio_set_value(gpio, value);
-
-	offset = group_offset[group];
-	switch (group) {
-	case 5:		/* GPF */
-	case 8:		/* GPI */
-	case 9:		/* GPJ */
-	case 13:	/* GPN */
-	case 14:	/* GPO */
-	case 15:	/* GPP */
-	case 16:	/* GPQ */
-		gpio_direction_output_2b(offset, bit << 1);
-		break;
-	default:
-		gpio_direction_output_4b(offset, bit << 2);
-	}
-
-	return 0;
-}
-
-/* one register, 2 bits per function -> GPF, GPI, GPJ, GPN, GPO, GPP, GPQ */
-static void s3c_d2pins(unsigned offset, unsigned pin_mode)
-{
-	unsigned bit = GET_BIT(pin_mode);
-	unsigned func = GET_FUNC(pin_mode);
-	unsigned reg;
-
-	if (PUD_PRESENT(pin_mode)) {
-		reg = readl(S3C_GPAPUD + offset);
-		reg &= ~(PUD_MASK << bit);
-		reg |= GET_PUD(pin_mode) << bit;
-		writel(reg, S3C_GPAPUD + offset);
-	}
-
-	/* in the case of pin's function is GPIO it also sets up the direction */
-	reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
-	writel(reg | (func << bit), S3C_GPACON + offset);
-
-	if (func == 1) { /* output? if yes, also set the initial value */
-		reg = readl(S3C_GPADAT + offset) & ~(1 << (bit >> 1));
-		reg |= GET_GPIOVAL(pin_mode) << (bit >> 1);
-		writel(reg, S3C_GPADAT + offset);
-	}
-}
-
-/* one register, 4 bits per function -> GPA, GPB, GPC, GPD, GPE, GPG, GPM */
-static void s3c_d4pins(unsigned offset, unsigned pin_mode)
-{
-	unsigned bit = GET_BIT(pin_mode);
-	unsigned func = GET_FUNC(pin_mode);
-	unsigned reg;
-
-	if (PUD_PRESENT(pin_mode)) {
-		reg = readl(S3C_GPAPUD + offset);
-		reg &= ~(PUD_MASK << (bit >> 1));
-		reg |= GET_PUD(pin_mode) << (bit >> 1);
-		writel(reg, S3C_GPAPUD + offset);
-	}
-
-	/* in the case of pin's function is GPIO it also sets up the direction */
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	writel(reg | (func << bit), S3C_GPACON + offset);
-
-	if (func == 1) { /* output? if yes, also set the initial value */
-		reg = readl(S3C_GPADAT + offset) & ~(1 << (bit >> 2));
-		reg |= GET_GPIOVAL(pin_mode) << (bit >> 2);
-		writel(reg, S3C_GPADAT + offset);
-	}
-}
-
-/* two registers, 4 bits per pin -> GPH, GPK, GPL */
-static void s3c_d42pins(unsigned offset, unsigned pin_mode)
-{
-	unsigned bit = GET_BIT(pin_mode);
-	unsigned func = GET_FUNC(pin_mode);
-	uint32_t reg;
-	unsigned reg_offs = 0;
-
-	if (PUD_PRESENT(pin_mode)) {
-		reg = readl(S3C_GPAPUD + 4 + offset);
-		reg &= ~(PUD_MASK << (bit >> 1));
-		reg |= GET_PUD(pin_mode) << (bit >> 1);
-		writel(reg, S3C_GPACON + 4 + offset);
-	}
-
-	if (bit > 31) {
-		reg_offs = 4;
-		bit -= 32;
-	}
-
-	/* in the case of pin's function is GPIO it also sets up the direction */
-	reg = readl(S3C_GPACON + offset + reg_offs) & ~(0xf << bit);
-	writel(reg | (func << bit), S3C_GPACON + offset + reg_offs);
-
-	if (func == 1) { /* output? if yes, also set the initial value */
-		reg = readl(S3C_GPADAT + 4 + offset) & ~(1 << (bit >> 2));
-		reg |= GET_GPIOVAL(pin_mode) << (bit >> 2);
-		writel(reg, S3C_GPADAT + 4 + offset);
-	}
-}
-
-/* 'gpio_mode' must be one of the 'GP?_*' macros */
-void s3c_gpio_mode(unsigned gpio_mode)
-{
-	unsigned group, offset;
-
-	group = GET_GROUP(gpio_mode);
-	offset = group_offset[group];
-
-	switch (group) {
-	case 5:		/* GPF */
-	case 8:		/* GPI */
-	case 9:		/* GPJ */
-	case 13:	/* GPN */
-	case 14:	/* GPO */
-	case 15:	/* GPP */
-	case 16:	/* GPQ */
-		s3c_d2pins(offset, gpio_mode);
-		break;
-	case 7:		/* GPH */
-	case 10:	/* GPK */
-	case 11:	/* GPL */
-		s3c_d42pins(offset, gpio_mode);
-		break;
-	default:
-		s3c_d4pins(offset, gpio_mode);
-	}
-}
diff --git a/arch/arm/mach-samsung/gpio-s5pcxx.c b/arch/arm/mach-samsung/gpio-s5pcxx.c
deleted file mode 100644
index 1a422f1746..0000000000
--- a/arch/arm/mach-samsung/gpio-s5pcxx.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- * Copyright (C) 2012 Juergen Beisert, Pengutronix
- *
- * This codes bases partially on code from the Linux kernel:
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *	http://armlinux.simtec.co.uk/
- *	Ben Dooks <ben at simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <errno.h>
-#include <io.h>
-#include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/s3c-iomap.h>
-
-#define S3C_GPACON (S3C_GPIO_BASE)
-#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
-#define S3C_GPAPUD (S3C_GPIO_BASE + 0x08)
-
-static inline unsigned group_offset(unsigned group)
-{
-    return group * 0x20;
-}
-
-void gpio_set_value(unsigned gpio, int value)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset = group_offset(group);
-	uint32_t reg;
-
-	reg = readl(S3C_GPADAT + offset);
-	reg &= ~(1 << bit);
-	reg |= (!!value) << bit;
-	writel(reg, S3C_GPADAT + offset);
-}
-
-int gpio_get_value(unsigned gpio)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset = group_offset(group);
-	uint32_t reg;
-
-	/* value */
-	reg = readl(S3C_GPADAT + offset);
-
-	return !!(reg & (1 << bit));
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset = group_offset(group);
-	uint32_t reg;
-
-	bit <<= 2;
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	writel(reg, S3C_GPACON + offset);
-
-	return 0;
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset = group_offset(group);
-	uint32_t reg;
-
-	gpio_set_value(gpio, value);
-
-	bit <<= 2;
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	reg |= 0x1 << bit;
-	writel(reg, S3C_GPACON + offset);
-
-	return 0;
-}
-
-
-/* 'gpio_mode' must be one of the 'GP?_*' macros */
-void s3c_gpio_mode(unsigned gpio_mode)
-{
-	unsigned group = GET_GROUP(gpio_mode);
-	unsigned bit = GET_BIT(gpio_mode);
-	unsigned func = GET_FUNC(gpio_mode);
-	unsigned offset = group_offset(group);
-	unsigned reg;
-
-	bit <<= 1;
-	if (PUD_PRESENT(gpio_mode)) {
-		reg = readl(S3C_GPAPUD + offset);
-		reg &= ~(PUD_MASK << bit);
-		reg |= GET_PUD(gpio_mode) << bit;
-		writel(reg, S3C_GPAPUD + offset);
-	}
-
-	bit <<= 1;
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	writel(reg | (func << bit), S3C_GPACON + offset);
-
-	if (func == 1) { /* output? if yes, also set the initial value */
-		reg = readl(S3C_GPADAT + offset) & ~(1 << (bit >> 2));
-		reg |= GET_GPIOVAL(gpio_mode) << (bit >> 2);
-		writel(reg, S3C_GPADAT + offset);
-	}
-
-}
diff --git a/arch/arm/mach-samsung/include/mach/bbu.h b/arch/arm/mach-samsung/include/mach/bbu.h
deleted file mode 100644
index ddc72a622d..0000000000
--- a/arch/arm/mach-samsung/include/mach/bbu.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __MACH_BBU_H
-#define __MACH_BBU_H
-
-#include <bbu.h>
-#include <errno.h>
-
-#ifdef CONFIG_BAREBOX_UPDATE_NAND_S3C24XX
-int s3c24x0_bbu_nand_register_handler(void);
-#else
-static inline int s3c24x0_bbu_nand_register_handler(void)
-{
-	return -ENOSYS;
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h b/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
deleted file mode 100644
index 51fd9a1825..0000000000
--- a/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef INCLUDE_MACH_DEVICES_S3C24XX_H
-# define INCLUDE_MACH_DEVICES_S3C24XX_H
-
-#include <driver.h>
-#include <mach/s3c24xx-iomap.h>
-#include <mach/s3c24xx-nand.h>
-#include <mach/s3c-mci.h>
-#include <mach/s3c24xx-fb.h>
-
-static inline void s3c24xx_add_nand(struct s3c24x0_nand_platform_data *d)
-{
-	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL,
-				S3C24X0_NAND_BASE, 0x80, IORESOURCE_MEM, d);
-}
-
-static inline void s3c24xx_add_mci(struct s3c_mci_platform_data *d)
-{
-	add_generic_device("s3c_mci", DEVICE_ID_DYNAMIC, NULL,
-				S3C2410_SDI_BASE, 0x80, IORESOURCE_MEM, d);
-}
-
-static inline void s3c24xx_add_fb(struct s3c_fb_platform_data *d)
-{
-	add_generic_device("s3c_fb", DEVICE_ID_DYNAMIC, NULL,
-				S3C2410_LCD_BASE, 0x80, IORESOURCE_MEM, d);
-}
-
-static inline void s3c24xx_add_ohci(void)
-{
-	add_generic_device("ohci", DEVICE_ID_DYNAMIC, NULL,
-			S3C2410_USB_HOST_BASE, 0x100, IORESOURCE_MEM, NULL);
-}
-
-static inline void s3c24xx_add_uart1(void)
-{
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
-			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
-}
-
-#endif /* INCLUDE_MACH_DEVICES_S3C24XX_H */
diff --git a/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h b/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h
deleted file mode 100644
index bcbee972e6..0000000000
--- a/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef INCLUDE_MACH_DEVICES_S3C64XX_H
-# define INCLUDE_MACH_DEVICES_S3C64XX_H
-
-#include <driver.h>
-#include <mach/s3c64xx-iomap.h>
-
-static inline void s3c64xx_add_uart1(void)
-{
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
-			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
-}
-
-static inline void s3c64xx_add_uart2(void)
-{
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART2_BASE,
-			S3C_UART2_SIZE, IORESOURCE_MEM, NULL);
-}
-
-static inline void s3c64xx_add_uart3(void)
-{
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART3_BASE,
-			S3C_UART3_SIZE, IORESOURCE_MEM, NULL);
-}
-
-#endif /* INCLUDE_MACH_DEVICES_S3C64XX_H */
diff --git a/arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h b/arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h
deleted file mode 100644
index b042505f25..0000000000
--- a/arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/*
- * Copyright (C) 2010 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_IOMUX_S3C24x0_H
-#define __MACH_IOMUX_S3C24x0_H
-
-/* 3322222222221111111111
- * 10987654321098765432109876543210
- *                            ^^^^^_ Bit offset
- *                        ^^^^______ Group Number
- *                    ^^____________ Function
- *                   ^______________ initial GPIO out value
- *                  ^_______________ Pull up feature present
- *                 ^________________ initial pull up setting
- */
-
-
-#define PIN(group,bit) (group * 32 + bit)
-#define FUNC(x) (((x) & 0x3) << 11)
-#define GET_FUNC(x) (((x) >> 11) & 0x3)
-#define GET_GROUP(x) (((x) >> 5) & 0xf)
-#define GET_BIT(x) (((x) & 0x1ff) % 32)
-#define GET_GPIOVAL(x) (((x) >> 13) & 0x1)
-#define GET_GPIO_NO(x) ((x & 0x1ff))
-#define GPIO_OUT FUNC(1)
-#define GPIO_IN FUNC(0)
-#define GPIO_VAL(x) ((!!(x)) << 13)
-#define PU (1 << 14)
-#define PU_PRESENT(x) (!!((x) & (1 << 14)))
-#define ENABLE_PU (0 << 15)
-#define DISABLE_PU (1 << 15)
-#define GET_PU(x) (!!((x) & DISABLE_PU))
-
-/*
- * Group 0: GPIO 0...31
- * Used GPIO: 0...22
- * These pins can also act as GPIO outputs
- */
-#define GPA0_ADDR0		(PIN(0,0) | FUNC(2))
-#define GPA0_ADDR0_GPIO		(PIN(0,0) | FUNC(0))
-#define GPA1_ADDR16		(PIN(0,1) | FUNC(2))
-#define GPA1_ADDR16_GPIO	(PIN(0,1) | FUNC(0))
-#define GPA2_ADDR17		(PIN(0,2) | FUNC(2))
-#define GPA2_ADDR17_GPIO	(PIN(0,2) | FUNC(0))
-#define GPA3_ADDR18		(PIN(0,3) | FUNC(2))
-#define GPA3_ADDR18_GPIO	(PIN(0,3) | FUNC(0))
-#define GPA4_ADDR19		(PIN(0,4) | FUNC(2))
-#define GPA4_ADDR19_GPIO	(PIN(0,4) | FUNC(0))
-#define GPA5_ADDR20		(PIN(0,5) | FUNC(2))
-#define GPA5_ADDR20_GPIO	(PIN(0,5) | FUNC(0))
-#define GPA6_ADDR21		(PIN(0,6) | FUNC(2))
-#define GPA6_ADDR21_GPIO	(PIN(0,6) | FUNC(0))
-#define GPA7_ADDR22		(PIN(0,7) | FUNC(2))
-#define GPA7_ADDR22_GPIO	(PIN(0,7) | FUNC(0))
-#define GPA8_ADDR23		(PIN(0,8) | FUNC(2))
-#define GPA8_ADDR23_GPIO	(PIN(0,8) | FUNC(0))
-#define GPA9_ADDR24		(PIN(0,9) | FUNC(2))
-#define GPA9_ADDR24_GPIO	(PIN(0,9) | FUNC(0))
-#define GPA10_ADDR25		(PIN(0,10) | FUNC(2))
-#define GPA10_ADDR25_GPIO	(PIN(0,10) | FUNC(0))
-#define GPA11_ADDR26		(PIN(0,11) | FUNC(2))
-#define GPA11_ADDR26_GPIO	(PIN(0,11) | FUNC(0))
-#define GPA12_NGCS1		(PIN(0,12) | FUNC(2))
-#define GPA12_NGCS1_GPIO	(PIN(0,12) | FUNC(0))
-#define GPA13_NGCS2		(PIN(0,13) | FUNC(2))
-#define GPA13_NGCS2_GPIO	(PIN(0,13) | FUNC(0))
-#define GPA14_NGCS3		(PIN(0,14) | FUNC(2))
-#define GPA14_NGCS3_GPIO	(PIN(0,14) | FUNC(0))
-#define GPA15_NGCS4		(PIN(0,15) | FUNC(2))
-#define GPA15_NGCS4_GPIO	(PIN(0,15) | FUNC(0))
-#define GPA16_NGCS5		(PIN(0,16) | FUNC(2))
-#define GPA16_NGCS5_GPIO	(PIN(0,16) | FUNC(0))
-#define GPA17_CLE		(PIN(0,17) | FUNC(2))
-#define GPA17_CLE_GPIO		(PIN(0,17) | FUNC(0))
-#define GPA18_ALE		(PIN(0,18) | FUNC(2))
-#define GPA18_ALE_GPIO		(PIN(0,18) | FUNC(0))
-#define GPA19_NFWE		(PIN(0,19) | FUNC(2))
-#define GPA19_NFWE_GPIO		(PIN(0,19) | FUNC(0))
-#define GPA20_NFRE		(PIN(0,20) | FUNC(2))
-#define GPA20_NFRE_GPIO		(PIN(0,20) | FUNC(0))
-#define GPA21_NRSTOUT		(PIN(0,21) | FUNC(2))
-#define GPA21_NRSTOUT_GPIO	(PIN(0,21) | FUNC(0))
-#define GPA22_NFCE		(PIN(0,22) | FUNC(2))
-#define GPA22_NFCE_GPIO		(PIN(0,22) | FUNC(0))
-
-/*
- * Group 1: GPIO 32...63
- * Used GPIO: 0...10
- * these pins can also act as GPIO inputs/outputs
- */
-#define GPB0_TOUT0	(PIN(1,0) | FUNC(2) | PU)
-#define GPB0_GPIO	(PIN(1,0) | FUNC(0) | PU)
-#define GPB1_TOUT1	(PIN(1,1) | FUNC(2) | PU)
-#define GPB1_GPIO	(PIN(1,1) | FUNC(0) | PU)
-#define GPB2_TOUT2	(PIN(1,2) | FUNC(2) | PU)
-#define GPB2_GPIO	(PIN(1,2) | FUNC(0) | PU)
-#define GPB3_TOUT3	(PIN(1,3) | FUNC(2) | PU)
-#define GPB3_GPIO	(PIN(1,3) | FUNC(0) | PU)
-#define GPB4_TCLK0	(PIN(1,4) | FUNC(2) | PU)
-#define GPB4_GPIO	(PIN(1,4) | FUNC(0) | PU)
-#define GPB5_NXBACK	(PIN(1,5) | FUNC(2) | PU)
-#define GPB5_GPIO	(PIN(1,5) | FUNC(0) | PU)
-#define GPB6_NXBREQ	(PIN(1,6) | FUNC(2) | PU)
-#define GPB6_GPIO	(PIN(1,6) | FUNC(0) | PU)
-#define GPB7_NXDACK1	(PIN(1,7) | FUNC(2) | PU)
-#define GPB7_GPIO	(PIN(1,7) | FUNC(0) | PU)
-#define GPB8_NXDREQ1	(PIN(1,8) | FUNC(2) | PU)
-#define GPB8_GPIO	(PIN(1,8) | FUNC(0) | PU)
-#define GPB9_NXDACK0	(PIN(1,9) | FUNC(2) | PU)
-#define GPB9_GPIO	(PIN(1,9) | FUNC(0) | PU)
-#define GPB10_NXDREQ0	(PIN(1,10) | FUNC(2) | PU)
-#define GPB10_GPIO	(PIN(1,10) | FUNC(0) | PU)
-
-/*
- * Group 1: GPIO 64...95
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPC0_LEND	(PIN(2,0) | FUNC(2) | PU)
-#define GPC0_GPIO	(PIN(2,0) | FUNC(0) | PU)
-#define GPC1_VCLK	(PIN(2,1) | FUNC(2) | PU)
-#define GPC1_GPIO	(PIN(2,1) | FUNC(0) | PU)
-#define GPC2_VLINE	(PIN(2,2) | FUNC(2) | PU)
-#define GPC2_GPIO	(PIN(2,2) | FUNC(0) | PU)
-#define GPC3_VFRAME	(PIN(2,3) | FUNC(2) | PU)
-#define GPC3_GPIO	(PIN(2,3) | FUNC(0) | PU)
-#define GPC4_VM		(PIN(2,4) | FUNC(2) | PU)
-#define GPC4_GPIO	(PIN(2,4) | FUNC(0) | PU)
-#define GPC5_LPCOE	(PIN(2,5) | FUNC(2) | PU)
-#define GPC5_GPIO	(PIN(2,5) | FUNC(0) | PU)
-#define GPC6_LPCREV	(PIN(2,6) | FUNC(2) | PU)
-#define GPC6_GPIO	(PIN(2,6) | FUNC(0) | PU)
-#define GPC7_LPCREVB	(PIN(2,7) | FUNC(2) | PU)
-#define GPC7_GPIO	(PIN(2,7) | FUNC(0) | PU)
-#define GPC8_VD0	(PIN(2,8) | FUNC(2) | PU)
-#define GPC8_GPIO	(PIN(2,8) | FUNC(0) | PU)
-#define GPC9_VD1	(PIN(2,9) | FUNC(2) | PU)
-#define GPC9_GPIO	(PIN(2,9) | FUNC(0) | PU)
-#define GPC10_VD2	(PIN(2,10) | FUNC(2) | PU)
-#define GPC10_GPIO	(PIN(2,10) | FUNC(0) | PU)
-#define GPC11_VD3	(PIN(2,11) | FUNC(2) | PU)
-#define GPC11_GPIO	(PIN(2,11) | FUNC(0) | PU)
-#define GPC12_VD4	(PIN(2,12) | FUNC(2) | PU)
-#define GPC12_GPIO	(PIN(2,12) | FUNC(0) | PU)
-#define GPC13_VD5	(PIN(2,13) | FUNC(2) | PU)
-#define GPC13_GPIO	(PIN(2,13) | FUNC(0) | PU)
-#define GPC14_VD6	(PIN(2,14) | FUNC(2) | PU)
-#define GPC14_GPIO	(PIN(2,14) | FUNC(0) | PU)
-#define GPC15_VD7	(PIN(2,15) | FUNC(2) | PU)
-#define GPC15_GPIO	(PIN(2,15) | FUNC(0) | PU)
-
-/*
- * Group 1: GPIO 96...127
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPD0_VD8	(PIN(3,0) | FUNC(2) | PU)
-#define GPD0_GPIO	(PIN(3,0) | FUNC(0) | PU)
-#define GPD1_VD9	(PIN(3,1) | FUNC(2) | PU)
-#define GPD1_GPIO	(PIN(3,1) | FUNC(0) | PU)
-#define GPD2_VD10	(PIN(3,2) | FUNC(2) | PU)
-#define GPD2_GPIO	(PIN(3,2) | FUNC(0) | PU)
-#define GPD3_VD11	(PIN(3,3) | FUNC(2) | PU)
-#define GPD3_GPIO	(PIN(3,3) | FUNC(0) | PU)
-#define GPD4_VD12	(PIN(3,4) | FUNC(2) | PU)
-#define GPD4_GPIO	(PIN(3,4) | FUNC(0) | PU)
-#define GPD5_VD13	(PIN(3,5) | FUNC(2) | PU)
-#define GPD5_GPIO	(PIN(3,5) | FUNC(0) | PU)
-#define GPD6_VD14	(PIN(3,6) | FUNC(2) | PU)
-#define GPD6_GPIO	(PIN(3,6) | FUNC(0) | PU)
-#define GPD7_VD15	(PIN(3,7) | FUNC(2) | PU)
-#define GPD7_GPIO	(PIN(3,7) | FUNC(0) | PU)
-#define GPD8_VD16	(PIN(3,8) | FUNC(2) | PU)
-#define GPD8_GPIO	(PIN(3,8) | FUNC(0) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPD8_SPIMISO1	(PIN(3,8) | FUNC(3) | PU)
-#endif
-#define GPD9_VD17	(PIN(3,9) | FUNC(2) | PU)
-#define GPD9_GPIO	(PIN(3,9) | FUNC(0) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPD9_SPIMOSI1	(PIN(3,9) | FUNC(3) | PU)
-#endif
-#define GPD10_VD18	(PIN(3,10) | FUNC(2) | PU)
-#define GPD10_GPIO	(PIN(3,10) | FUNC(0) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPD10_SPICLK	(PIN(3,10) | FUNC(3) | PU)
-#endif
-#define GPD11_VD19	(PIN(3,11) | FUNC(2) | PU)
-#define GPD11_GPIO	(PIN(3,11) | FUNC(0) | PU)
-#define GPD12_VD20	(PIN(3,12) | FUNC(2) | PU)
-#define GPD12_GPIO	(PIN(3,12) | FUNC(0) | PU)
-#define GPD13_VD21	(PIN(3,13) | FUNC(2) | PU)
-#define GPD13_GPIO	(PIN(3,13) | FUNC(0) | PU)
-#define GPD14_VD22	(PIN(3,14) | FUNC(2) | PU)
-#define GPD14_GPIO	(PIN(3,14) | FUNC(0) | PU)
-#define GPD14_NSS1	(PIN(3,14) | FUNC(3) | PU)
-#define GPD15_VD23	(PIN(3,15) | FUNC(2) | PU)
-#define GPD15_GPIO	(PIN(3,15) | FUNC(0) | PU)
-#define GPD15_NSS0	(PIN(3,15) | FUNC(3) | PU)
-
-/*
- * Group 1: GPIO 128...159
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPE0_I2SLRCK	(PIN(4,0) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE0_AC_SYNC	(PIN(4,0) | FUNC(3) | PU)
-#endif
-#define GPE0_GPIO	(PIN(4,0) | FUNC(0) | PU)
-#define GPE1_I2SSCLK	(PIN(4,1) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE1_AC_BIT_CLK (PIN(4,1) | FUNC(3) | PU)
-#endif
-#define GPE1_GPIO	(PIN(4,1) | FUNC(0) | PU)
-#define GPE2_CDCLK	(PIN(4,2) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE2_AC_NRESET	(PIN(4,2) | FUNC(3) | PU)
-#endif
-#define GPE2_GPIO	(PIN(4,2) | FUNC(0) | PU)
-#define GPE3_I2SDI	(PIN(4,3) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE3_AC_SDATA_IN (PIN(4,3) | FUNC(3) | PU)
-#endif
-#ifdef CONFIG_CPU_S3C2410
-# define GPE_NSS0	(PIN(4,3) | FUNC(3) | PU)
-#endif
-#define GPE3_GPIO	(PIN(4,3) | FUNC(0) | PU)
-#define GPE4_I2SDO	(PIN(4,4) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE4_AC_SDATA_OUT (PIN(4,4) | FUNC(3) | PU)
-#endif
-#ifdef CONFIG_CPU_S3C2440
-# define GPE4_I2SSDI	(PIN(4,4) | FUNC(3) | PU)
-#endif
-#define GPE4_GPIO	(PIN(4,4) | FUNC(0) | PU)
-#define GPE5_SDCLK	(PIN(4,5) | FUNC(2) | PU)
-#define GPE5_GPIO	(PIN(4,5) | FUNC(0) | PU)
-#define GPE6_SDCMD	(PIN(4,6) | FUNC(2) | PU)
-#define GPE6_GPIO	(PIN(4,6) | FUNC(0) | PU)
-#define GPE7_SDDAT0	(PIN(4,7) | FUNC(2) | PU)
-#define GPE7_GPIO	(PIN(4,7) | FUNC(0) | PU)
-#define GPE8_SDDAT1	(PIN(4,8) | FUNC(2) | PU)
-#define GPE8_GPIO	(PIN(4,8) | FUNC(0) | PU)
-#define GPE9_SDDAT2	(PIN(4,9) | FUNC(2) | PU)
-#define GPE9_GPIO	(PIN(4,9) | FUNC(0) | PU)
-#define GPE10_SDDAT3	(PIN(4,10) | FUNC(2) | PU)
-#define GPE10_GPIO	(PIN(4,10) | FUNC(0) | PU)
-#define GPE11_SPIMISO0	(PIN(4,11) | FUNC(2) | PU)
-#define GPE11_GPIO	(PIN(4,11) | FUNC(0) | PU)
-#define GPE12_SPIMOSI0	(PIN(4,12) | FUNC(2) | PU)
-#define GPE12_GPIO	(PIN(4,12) | FUNC(0) | PU)
-#define GPE13_SPICLK0	(PIN(4,13) | FUNC(2) | PU)
-#define GPE13_GPIO	(PIN(4,13) | FUNC(0) | PU)
-#define GPE14_IICSCL	(PIN(4,14) | FUNC(2))	/* no pullup option */
-#define GPE14_GPIO	(PIN(4,14) | FUNC(0))	/* no pullup option */
-#define GPE15_IICSDA	(PIN(4,15) | FUNC(2))	/* no pullup option */
-#define GPE15_GPIO	(PIN(4,15) | FUNC(0))	/* no pullup option */
-
-/*
- * Group 1: GPIO 160...191
- * Used GPIO: 0...7
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPF0_EINT0	(PIN(5,0) | FUNC(2) | PU)
-#define GPF0_GPIO	(PIN(5,0) | FUNC(0) | PU)
-#define GPF1_EINT1	(PIN(5,1) | FUNC(2) | PU)
-#define GPF1_GPIO	(PIN(5,1) | FUNC(0) | PU)
-#define GPF2_EINT2	(PIN(5,2) | FUNC(2) | PU)
-#define GPF2_GPIO	(PIN(5,2) | FUNC(0) | PU)
-#define GPF3_EINT3	(PIN(5,3) | FUNC(2) | PU)
-#define GPF3_GPIO	(PIN(5,3) | FUNC(0) | PU)
-#define GPF4_EINT4	(PIN(5,4) | FUNC(2) | PU)
-#define GPF4_GPIO	(PIN(5,4) | FUNC(0) | PU)
-#define GPF5_EINT5	(PIN(5,5) | FUNC(2) | PU)
-#define GPF5_GPIO	(PIN(5,5) | FUNC(0) | PU)
-#define GPF6_EINT6	(PIN(5,6) | FUNC(2) | PU)
-#define GPF6_GPIO	(PIN(5,6) | FUNC(0) | PU)
-#define GPF7_EINT7	(PIN(5,7) | FUNC(2) | PU)
-#define GPF7_GPIO	(PIN(5,7) | FUNC(0) | PU)
-
-/*
- * Group 1: GPIO 192..223
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPG0_EINT8	(PIN(6,0) | FUNC(2) | PU)
-#define GPG0_GPIO	(PIN(6,0) | FUNC(0) | PU)
-#define GPG1_EINT9	(PIN(6,1) | FUNC(2) | PU)
-#define GPG1_GPIO	(PIN(6,1) | FUNC(0) | PU)
-#define GPG2_EINT10	(PIN(6,2) | FUNC(2) | PU)
-#define GPG2_NSS0	(PIN(6,2) | FUNC(3) | PU)
-#define GPG2_GPIO	(PIN(6,2) | FUNC(0) | PU)
-#define GPG3_EINT11	(PIN(6,3) | FUNC(2) | PU)
-#define GPG3_NSS1	(PIN(6,3) | FUNC(3) | PU)
-#define GPG3_GPIO	(PIN(6,3) | FUNC(0) | PU)
-#define GPG4_EINT12	(PIN(6,4) | FUNC(2) | PU)
-#define GPG4_LCD_PWREN	(PIN(6,4) | FUNC(3) | PU)
-#define GPG4_GPIO	(PIN(6,4) | FUNC(0) | PU)
-#define GPG5_EINT13	(PIN(6,5) | FUNC(2) | PU)
-#define GPG5_SPIMISO1	(PIN(6,5) | FUNC(3) | PU)
-#define GPG5_GPIO	(PIN(6,5) | FUNC(0) | PU)
-#define GPG6_EINT14	(PIN(6,6) | FUNC(2) | PU)
-#define GPG6_SPIMOSI1	(PIN(6,6) | FUNC(3) | PU)
-#define GPG6_GPIO	(PIN(6,6) | FUNC(0) | PU)
-#define GPG7_EINT15	(PIN(6,7) | FUNC(2) | PU)
-#define GPG7_SPICLK1	(PIN(6,7) | FUNC(3) | PU)
-#define GPG7_GPIO	(PIN(6,7) | FUNC(0) | PU)
-#define GPG8_EINT16	(PIN(6,8) | FUNC(2) | PU)
-#define GPG8_GPIO	(PIN(6,8) | FUNC(0) | PU)
-#define GPG9_EINT17	(PIN(6,9) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPG9_NRTS1	(PIN(6,9) | FUNC(3) | PU)
-#endif
-#define GPG9_GPIO	(PIN(6,9) | FUNC(0) | PU)
-#define GPG10_EINT18	(PIN(6,10) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPG10_NCTS1	(PIN(6,10) | FUNC(3) | PU)
-#endif
-#define GPG10_GPIO	(PIN(6,10) | FUNC(0) | PU)
-#define GPG11_EINT19	(PIN(6,11) | FUNC(2) | PU)
-#define GPG11_TCLK	(PIN(6,11) | FUNC(3) | PU)
-#define GPG11_GPIO	(PIN(6,11) | FUNC(0) | PU)
-#define GPG12_EINT20	(PIN(6,12) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG12_XMON	(PIN(6,12) | FUNC(3) | PU)
-#endif
-#define GPG12_GPIO	(PIN(6,12) | FUNC(0) | PU)
-#define GPG13_EINT21	(PIN(6,13) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG13_NXPON	(PIN(6,13) | FUNC(3) | PU)
-#endif
-#define GPG13_GPIO	(PIN(6,13) | FUNC(0) | PU)	/* must be input in NAND boot mode */
-#define GPG14_EINT22	(PIN(6,14) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG14_YMON	(PIN(6,14) | FUNC(3) | PU)
-#endif
-#define GPG14_GPIO	(PIN(6,14) | FUNC(0) | PU)	/* must be input in NAND boot mode */
-#define GPG15_EINT23	(PIN(6,15) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG15_YPON	(PIN(6,15) | FUNC(3) | PU)
-#endif
-#define GPG15_GPIO	(PIN(6,15) | FUNC(0) | PU)	/* must be input in NAND boot mode */
-
-/*
- * Group 1: GPIO 224..255
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPH0_NCTS0	(PIN(7,0) | FUNC(2) | PU)
-#define GPH0_GPIO	(PIN(7,0) | FUNC(0) | PU)
-#define GPH1_NRTS0	(PIN(7,1) | FUNC(2) | PU)
-#define GPH1_GPIO	(PIN(7,1) | FUNC(0) | PU)
-#define GPH2_TXD0	(PIN(7,2) | FUNC(2) | PU)
-#define GPH2_GPIO	(PIN(7,2) | FUNC(0) | PU)
-#define GPH3_RXD0	(PIN(7,3) | FUNC(2) | PU)
-#define GPH3_GPIO	(PIN(7,3) | FUNC(0) | PU)
-#define GPH4_TXD1	(PIN(7,4) | FUNC(2) | PU)
-#define GPH4_GPIO	(PIN(7,4) | FUNC(0) | PU)
-#define GPH5_RXD1	(PIN(7,5) | FUNC(2) | PU)
-#define GPH5_GPIO	(PIN(7,5) | FUNC(0) | PU)
-#define GPH6_TXD2	(PIN(7,6) | FUNC(2) | PU)
-#define GPH6_NRTS1	(PIN(7,6) | FUNC(3) | PU)
-#define GPH6_GPIO	(PIN(7,6) | FUNC(0) | PU)
-#define GPH7_RXD2	(PIN(7,7) | FUNC(2) | PU)
-#define GPH7_NCTS1	(PIN(7,7) | FUNC(3) | PU)
-#define GPH7_GPIO	(PIN(7,7) | FUNC(0) | PU)
-#define GPH8_UEXTCLK	(PIN(7,8) | FUNC(2) | PU)
-#define GPH8_GPIO	(PIN(7,8) | FUNC(0) | PU)
-#define GPH9_CLOCKOUT0	(PIN(7,9) | FUNC(2) | PU)
-#define GPH9_GPIO	(PIN(7,9) | FUNC(0) | PU)
-#define GPH10_CLKOUT1	(PIN(7,10) | FUNC(2) | PU)
-#define GPH10_GPIO	(PIN(7,10) | FUNC(0) | PU)
-
-#ifdef CONFIG_CPU_S3C2440
-/*
- * Group 1: GPIO 256..287
- * Used GPIO: 0...12
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPJ0_CAMDATA0	(PIN(8,0) | FUNC(2) | PU)
-#define GPJ0_GPIO	(PIN(8,0) | FUNC(0) | PU)
-#define GPJ1_CAMDATA1	(PIN(8,1) | FUNC(2) | PU)
-#define GPJ1_GPIO	(PIN(8,1) | FUNC(0) | PU)
-#define GPJ2_CAMDATA2	(PIN(8,2) | FUNC(2) | PU)
-#define GPJ2_GPIO	(PIN(8,2) | FUNC(0) | PU)
-#define GPJ3_CAMDATA3	(PIN(8,3) | FUNC(2) | PU)
-#define GPJ3_GPIO	(PIN(8,3) | FUNC(0) | PU)
-#define GPJ4_CAMDATA4	(PIN(8,4) | FUNC(2) | PU)
-#define GPJ4_GPIO	(PIN(8,4) | FUNC(0) | PU)
-#define GPJ5_CAMDATA5	(PIN(8,5) | FUNC(2) | PU)
-#define GPJ5_GPIO	(PIN(8,5) | FUNC(0) | PU)
-#define GPJ6_CAMDATA6	(PIN(8,6) | FUNC(2) | PU)
-#define GPJ6_GPIO	(PIN(8,6) | FUNC(0) | PU)
-#define GPJ7_CAMDATA7	(PIN(8,7) | FUNC(2) | PU)
-#define GPJ7_GPIO	(PIN(8,7) | FUNC(0) | PU)
-#define GPJ8_CAMPCLK	(PIN(8,8) | FUNC(2) | PU)
-#define GPJ8_GPIO	(PIN(8,8) | FUNC(0) | PU)
-#define GPJ9_CAMVSYNC	(PIN(8,9) | FUNC(2) | PU)
-#define GPJ9_GPIO	(PIN(8,9) | FUNC(0) | PU)
-#define GPJ10_CAMHREF	(PIN(8,10) | FUNC(2) | PU)
-#define GPJ10_GPIO	(PIN(8,10) | FUNC(0) | PU)
-#define GPJ11_CAMCLKOUT	(PIN(8,11) | FUNC(2) | PU)
-#define GPJ11_GPIO	(PIN(8,11) | FUNC(0) | PU)
-#define GPJ12_CAMRESET	(PIN(8,12) | FUNC(0) | PU)
-#define GPJ12_GPIO	(PIN(8,12) | FUNC(0) | PU)
-
-#endif
-
-#endif /* __MACH_IOMUX_S3C24x0_H */
diff --git a/arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h b/arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h
deleted file mode 100644
index 5d68b71ae7..0000000000
--- a/arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h
+++ /dev/null
@@ -1,542 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_IOMUX_S3C64XX_H
-# define __MACH_IOMUX_S3C64XX_H
-
-/* 3322222222221111111111
- * 10987654321098765432109876543210
- *                           ^^^^^^_ Bit offset
- *                      ^^^^^_______ Group Number
- *                  ^^^^____________ Function
- *                 ^________________ initial GPIO out value
- *                ^_________________ Pull up/down feature present
- *              ^^__________________ initial pull up/down setting
- */
-
-#define PIN(group,bit) ((group << 6) + bit)
-#define FUNC(x) (((x) & 0xf) << 11)
-#define GET_FUNC(x) (((x) >> 11) & 0xf)
-#define GET_GROUP(x) (((x) >> 6) & 0x1f)
-#define GET_BIT(x) ((x) & 0x3f)
-#define GET_GPIOVAL(x) (!!((x) & (1 << 15)))
-#define GPIO_OUT (1 << 11)
-#define GPIO_IN (0 << 11)
-#define GPIO_VAL(x) ((!!(x)) << 15)
-#define PUD_MASK 0x3
-#define PUD (1 << 16)
-#define PUD_PRESENT(x) (!!((x) & (1 << 16)))
-#define DISABLE_PUD (0 << 17)
-#define ENABLE_PU (2 << 17)
-#define ENABLE_PD (1 << 17)
-#define GET_PUD(x) (((x) >> 17) & PUD_MASK)
-
-/*
- * To have a chance for simple GPIO manipulation routines
- * define the GPIO numbers with a real simple scheme.
- *
- * Keep in mind: The 'GPIO_2_NO' creates a value to be used with the real gpio
- * routines and *not* for the multiplexer routines!
- */
-#define GPIO_2_NO(x,y) (PIN(x,y))
-
-/*
- * Group A: GPIO 0...7
- * Used GPIO: 0...7
- * These pins can also act as GPIO outputs
- */
-#define GPA0		(PIN(0,0) | PUD)
-#define GPA0_GPIO	(GPA0 | FUNC(0))
-#define GPA0_RXD0	(GPA0 | FUNC(2))
-#define GPA1		(PIN(0,4) | PUD)
-#define GPA1_GPIO	(GPA1 | FUNC(0))
-#define GPA1_TXD0	(GPA1 | FUNC(2))
-#define GPA2		(PIN(0,8) | PUD)
-#define GPA2_GPIO	(GPA2 | FUNC(0))
-#define GPA2_NCTS0	(GPA2 | FUNC(2))
-#define GPA3		(PIN(0,12) | PUD)
-#define GPA3_GPIO	(GPA3 | FUNC(0))
-#define GPA3_NRTS0	(GPA3 | FUNC(2))
-#define GPA4		(PIN(0,16) | PUD)
-#define GPA4_GPIO	(GPA4 | FUNC(0))
-#define GPA4_RXD1	(GPA4 | FUNC(2))
-#define GPA5		(PIN(0,20) | PUD)
-#define GPA5_GPIO	(GPA5 | FUNC(0))
-#define GPA5_TXD1	(GPA5 | FUNC(2))
-#define GPA6		(PIN(0,24) | PUD)
-#define GPA6_GPIO	(GPA6 | FUNC(0))
-#define GPA6_NCTS1	(GPA6 | FUNC(2))
-#define GPA7		(PIN(0,28) | PUD)
-#define GPA7_GPIO	(GPA7 | FUNC(0))
-#define GPA7_NRTS1	(GPA7 | FUNC(2))
-
-/*
- * Group B: GPIO 0...7
- * Used GPIO: 8...15
- * These pins can also act as GPIO outputs
- */
-#define GPB0		(PIN(1,0) | PUD)
-#define GPB0_GPIO	(GPB0 | FUNC(0))
-#define GPB0_RXD2	(GPB0 | FUNC(2))
-#define GPB0_DMAREQ	(GPB0 | FUNC(3))
-#define GPB0_IRDA_RXD	(GPB0 | FUNC(4))
-#define GPB0_ADDR_CF0	(GPB0 | FUNC(5))
-#define GPB1		(PIN(1,4) | PUD)
-#define GPB1_GPIO	(GPB1 | FUNC(0))
-#define GPB1_TXD2	(GPB1 | FUNC(2))
-#define GPB1_DMAREQ	(GPB1 | FUNC(3))
-#define GPB1_IRDA_TXD	(GPB1 | FUNC(4))
-#define GPB1_ADDR_CF1	(GPB1 | FUNC(5))
-#define GPB2		(PIN(1,8) | PUD)
-#define GPB2_GPIO	(GPB2 | FUNC(0))
-#define GPB2_RXD3	(GPB2 | FUNC(2))
-#define GPB2_IRDA_RXD	(GPB2 | FUNC(3))
-#define GPB2_DMAREQ	(GPB2 | FUNC(4))
-#define GPB2_ADDR_CF2	(GPB2 | FUNC(5))
-#define GPB2_IIC1_SCL	(GPB2 | FUNC(6))
-#define GPB3		(PIN(1,12) | PUD)
-#define GPB3_GPIO	(GPB3 | FUNC(0))
-#define GPB3_TXD3	(GPB3 | FUNC(2))
-#define GPB3_IRDA_TXD	(GPB3 | FUNC(3))
-#define GPB3_DMAREQ	(GPB3 | FUNC(4))
-#define GPB3_IIC1_SDA	(GPB3 | FUNC(6))
-#define GPB4		(PIN(1,16) | PUD)
-#define GPB4_GPIO	(GPB4 | FUNC(0))
-#define GPB4_SDBW	(GPB4 | FUNC(2))
-#define GPB4_CAM_FLD	(GPB4 | FUNC(3))
-#define GPB4_CF_DIR	(GPB4 | FUNC(4))
-#define GPB5		(PIN(1,20) | PUD)
-#define GPB5_GPIO	(GPB5 | FUNC(0))
-#define GPB5_IIC0_SCL	(GPB5 | FUNC(2))
-#define GPB6		(PIN(1,24) | PUD)
-#define GPB6_GPIO	(GPB6 | FUNC(0))
-#define GPB6_IIC0_SDA	(GPB6 | FUNC(2))
-
-#define GPC0		(PIN(2,0) | PUD)
-#define GPC0_GPIO	(GPC0 | FUNC(0))
-#define GPC0_SPI0_MISO	(GPC0 | FUNC(2))
-#define GPC1		(PIN(2,4) | PUD)
-#define GPC1_GPIO	(GPC1 | FUNC(0))
-#define GPC1_SPI0_CLK	(GPC1 | FUNC(2))
-#define GPC2		(PIN(2,8) | PUD)
-#define GPC2_GPIO	(GPC2 | FUNC(0))
-#define GPC2_SPI0_MOSI	(GPC2 | FUNC(2))
-#define GPC3		(PIN(2,12) | PUD)
-#define GPC3_GPIO	(GPC3 | FUNC(0))
-#define GPC3_SPI0_NCS	(GPC3 | FUNC(2))
-#define GPC4		(PIN(2,16) | PUD)
-#define GPC4_GPIO	(GPC4 | FUNC(0))
-#define GPC4_SPI1_MISO	(GPC4 | FUNC(2))
-#define GPC5		(PIN(2,20) | PUD)
-#define GPC5_GPIO	(GPC5 | FUNC(0))
-#define GPC5_SPI1_CLK	(GPC5 | FUNC(2))
-#define GPC6		(PIN(2,24) | PUD)
-#define GPC6_GPIO	(GPC6 | FUNC(0))
-#define GPC6_SPI1_MOSI	(GPC6 | FUNC(2))
-#define GPC7		(PIN(2,28) | PUD)
-#define GPC7_GPIO	(GPC7 | FUNC(0))
-#define GPC7_SPI1_NCS	(GPC7 | FUNC(2))
-
-#define GPD0		(PIN(3,0) | PUD)
-#define GPD0_AC97_BITCLK (GPD0 | FUNC(4))
-#define GPD1		(PIN(3,4) | PUD)
-#define GPD1_AC97_NRST	(GPD1 | FUNC(4))
-#define GPD2		(PIN(3,8) | PUD)
-#define GPD2_AC97_SYNC	(GPD2 | FUNC(4))
-#define GPD3		(PIN(3,12) | PUD)
-#define GPD3_AC97_SDI	(GPD3 | FUNC(4))
-#define GPD4		(PIN(3,16) | PUD)
-#define GPD4_AC97_SDO	(GPD4 | FUNC(4))
-
-#define GPE0		(PIN(4,0) | PUD)
-#define GPE0_GPIO	(GPE0 | FUNC(0))
-#define GPE1		(PIN(4,4) | PUD)
-#define GPE1_GPIO	(GPE1 | FUNC(0))
-#define GPE2		(PIN(4,8) | PUD)
-#define GPE2_GPIO	(GPE2 | FUNC(0))
-#define GPE3		(PIN(4,12) | PUD)
-#define GPE3_GPIO	(GPE3 | FUNC(0))
-#define GPE4		(PIN(4,16) | PUD)
-#define GPE4_GPIO	(GPE4 | FUNC(0))
-
-#define GPF0		(PIN(5,0) | PUD)
-#define GPF0_GPIO	(GPF0 | FUNC(0))
-#define GPF1		(PIN(5,2) | PUD)
-#define GPF1_GPIO	(GPF1 | FUNC(0))
-#define GPF2		(PIN(5,4) | PUD)
-#define GPF2_GPIO	(GPF2 | FUNC(0))
-#define GPF3		(PIN(5,6) | PUD)
-#define GPF3_GPIO	(GPF3 | FUNC(0))
-#define GPF4		(PIN(5,8) | PUD)
-#define GPF4_GPIO	(GPF4 | FUNC(0))
-#define GPF5		(PIN(5,10) | PUD)
-#define GPF5_GPIO	(GPF5 | FUNC(0))
-#define GPF6		(PIN(5,12) | PUD)
-#define GPF6_GPIO	(GPF6 | FUNC(0))
-#define GPF7		(PIN(5,14) | PUD)
-#define GPF7_GPIO	(GPF7 | FUNC(0))
-#define GPF8		(PIN(5,16) | PUD)
-#define GPF8_GPIO	(GPF8 | FUNC(0))
-#define GPF9		(PIN(5,18) | PUD)
-#define GPF9_GPIO	(GPF9 | FUNC(0))
-#define GPF10		(PIN(5,20) | PUD)
-#define GPF10_GPIO	(GPF10 | FUNC(0))
-#define GPF11		(PIN(5,22) | PUD)
-#define GPF11_GPIO	(GPF11 | FUNC(0))
-#define GPF12		(PIN(5,24) | PUD)
-#define GPF12_GPIO	(GPF12 | FUNC(0))
-#define GPF13		(PIN(5,26) | PUD)
-#define GPF13_GPIO	(GPF13 | FUNC(0))
-#define GPF14		(PIN(5,28) | PUD)
-#define GPF14_GPIO	(GPF14 | FUNC(0))
-#define GPF14_PWM0	(GPF14 | FUNC(2))
-#define GPF14_CLKOUT	(GPF14 | FUNC(3))
-#define GPF15		(PIN(5,30) | PUD)
-#define GPF15_GPIO	(GPF15 | FUNC(0))
-#define GPF15_PWM1	(GPF15 | FUNC(2))
-
-#define GPG0		(PIN(6,0) | PUD)
-#define GPG0_MMC0_CLK	(GPG0 | FUNC(2))
-#define GPG1		(PIN(6,4) | PUD)
-#define GPG1_MMC0_CMD	(GPG1 | FUNC(2))
-#define GPG2		(PIN(6,8) | PUD)
-#define GPG2_MMC0_DAT0	(GPG2 | FUNC(2))
-#define GPG3		(PIN(6,12) | PUD)
-#define GPG3_MMC0_DAT1	(GPG3 | FUNC(2))
-#define GPG4		(PIN(6,16) | PUD)
-#define GPG4_MMC0_DAT2	(GPG4 | FUNC(2))
-#define GPG5		(PIN(6,20) | PUD)
-#define GPG5_MMC0_DAT3	(GPG5 | FUNC(2))
-#define GPG6		(PIN(6,24) | PUD)
-#define GPG6_MMC0_NCD	(GPG6 | FUNC(2))
-
-#define GPH0		(PIN(7,0) | PUD)
-#define GPH0_GPIO	(GPH0 | FUNC(0))
-#define GPH1		(PIN(7,4) | PUD)
-#define GPH1_GPIO	(GPH1 | FUNC(0))
-#define GPH2		(PIN(7,8) | PUD)
-#define GPH2_GPIO	(GPH2 | FUNC(0))
-#define GPH3		(PIN(7,12) | PUD)
-#define GPH3_GPIO	(GPH3 | FUNC(0))
-#define GPH4		(PIN(7,16) | PUD)
-#define GPH4_GPIO	(GPH4 | FUNC(0))
-#define GPH5		(PIN(7,20) | PUD)
-#define GPH5_GPIO	(GPH5 | FUNC(0))
-#define GPH6		(PIN(7,24) | PUD)
-#define GPH6_GPIO	(GPH6 | FUNC(0))
-#define GPH7		(PIN(7,28) | PUD)
-#define GPH7_GPIO	(GPH7 | FUNC(0))
-#define GPH8		(PIN(7,32) | PUD)
-#define GPH8_GPIO	(GPH8 | FUNC(0))
-#define GPH9		(PIN(7,36) | PUD)
-#define GPH9_GPIO	(GPH9 | FUNC(0))
-
-#define GPI0		(PIN(8,0) | PUD)
-#define GPI0_GPIO	(GPI0 | FUNC(0))
-#define GPI1		(PIN(8,2) | PUD)
-#define GPI1_GPIO	(GPI1 | FUNC(0))
-#define GPI2		(PIN(8,4) | PUD)
-#define GPI2_GPIO	(GPI2 | FUNC(0))
-#define GPI3		(PIN(8,6) | PUD)
-#define GPI3_GPIO	(GPI3 | FUNC(0))
-#define GPI4		(PIN(8,8) | PUD)
-#define GPI4_GPIO	(GPI4 | FUNC(0))
-#define GPI5		(PIN(8,10) | PUD)
-#define GPI5_GPIO	(GPI5 | FUNC(0))
-#define GPI6		(PIN(8,12) | PUD)
-#define GPI6_GPIO	(GPI6 | FUNC(0))
-#define GPI7		(PIN(8,14) | PUD)
-#define GPI7_GPIO	(GPI7 | FUNC(0))
-#define GPI8		(PIN(8,16) | PUD)
-#define GPI8_GPIO	(GPI8 | FUNC(0))
-#define GPI9		(PIN(8,18) | PUD)
-#define GPI9_GPIO	(GPI9 | FUNC(0))
-#define GPI10		(PIN(8,20) | PUD)
-#define GPI10_GPIO	(GPI10 | FUNC(0))
-#define GPI11		(PIN(8,22) | PUD)
-#define GPI11_GPIO	(GPI11 | FUNC(0))
-#define GPI12		(PIN(8,24) | PUD)
-#define GPI12_GPIO	(GPI12 | FUNC(0))
-#define GPI13		(PIN(8,26) | PUD)
-#define GPI13_GPIO	(GPI13 | FUNC(0))
-#define GPI14		(PIN(8,28) | PUD)
-#define GPI14_GPIO	(GPI14 | FUNC(0))
-#define GPI15		(PIN(8,30) | PUD)
-#define GPI15_GPIO	(GPI15 | FUNC(0))
-
-#define GPJ0		(PIN(9,0) | PUD)
-#define GPJ0_GPIO	(GPJ0 | FUNC(0))
-#define GPJ1		(PIN(9,2) | PUD)
-#define GPJ1_GPIO	(GPJ1 | FUNC(0))
-#define GPJ2		(PIN(9,4) | PUD)
-#define GPJ2_GPIO	(GPJ2 | FUNC(0))
-#define GPJ3		(PIN(9,6) | PUD)
-#define GPJ3_GPIO	(GPJ3 | FUNC(0))
-#define GPJ4		(PIN(9,8) | PUD)
-#define GPJ4_GPIO	(GPJ4 | FUNC(0))
-#define GPJ5		(PIN(9,10) | PUD)
-#define GPJ5_GPIO	(GPJ5 | FUNC(0))
-#define GPJ6		(PIN(9,12) | PUD)
-#define GPJ6_GPIO	(GPJ6 | FUNC(0))
-#define GPJ7		(PIN(9,14) | PUD)
-#define GPJ7_GPIO	(GPJ7 | FUNC(0))
-#define GPJ8		(PIN(9,16) | PUD)
-#define GPJ8_GPIO	(GPJ8 | FUNC(0))
-#define GPJ9		(PIN(9,18) | PUD)
-#define GPJ9_GPIO	(GPJ9 | FUNC(0))
-#define GPJ10		(PIN(9,20) | PUD)
-#define GPJ10_GPIO	(GPJ10 | FUNC(0))
-#define GPJ11		(PIN(9,22) | PUD)
-#define GPJ11_GPIO	(GPJ11 | FUNC(0))
-
-#define GPK0		(PIN(10,0) | PUD)
-#define GPK0_DATA0	(GPK0 | FUNC(2))
-#define GPK0_GPIO	(GPK0 | FUNC(0))
-#define GPK1		(PIN(10,4) | PUD)
-#define GPK1_DATA1	(GPK1 | FUNC(2))
-#define GPK1_GPIO	(GPK1 | FUNC(0))
-#define GPK2		(PIN(10,8) | PUD)
-#define GPK2_DATA2	(GPK2 | FUNC(2))
-#define GPK2_GPIO	(GPK2 | FUNC(0))
-#define GPK3		(PIN(10,12) | PUD)
-#define GPK3_DATA3	(GPK3 | FUNC(2))
-#define GPK3_GPIO	(GPK3 | FUNC(0))
-#define GPK4		(PIN(10,16) | PUD)
-#define GPK4_DATA4	(GPK4 | FUNC(2))
-#define GPK4_GPIO	(GPK4 | FUNC(0))
-#define GPK5		(PIN(10,20) | PUD)
-#define GPK5_DATA5	(GPK5 | FUNC(2))
-#define GPK5_GPIO	(GPK5 | FUNC(0))
-#define GPK6		(PIN(10,24) | PUD)
-#define GPK6_DATA6	(GPK6 | FUNC(2))
-#define GPK6_GPIO	(GPK6 | FUNC(0))
-#define GPK7		(PIN(10,28) | PUD)
-#define GPK7_DATA7	(GPK7 | FUNC(2))
-#define GPK7_GPIO	(GPK7 | FUNC(0))
-#define GPK8		(PIN(10,32) | PUD)
-#define GPK8_DATA8	(GPK8 | FUNC(2))
-#define GPK8_GPIO	(GPK8 | FUNC(0))
-#define GPK9		(PIN(10,36) | PUD)
-#define GPK9_DATA9	(GPK9 | FUNC(2))
-#define GPK9_GPIO	(GPK9 | FUNC(0))
-#define GPK10		(PIN(10,40) | PUD)
-#define GPK10_DATA10	(GPK10 | FUNC(2))
-#define GPK10_GPIO	(GPK10 | FUNC(0))
-#define GPK11		(PIN(10,44) | PUD)
-#define GPK11_DATA11	(GPK11 | FUNC(2))
-#define GPK11_GPIO	(GPK11 | FUNC(0))
-#define GPK12		(PIN(10,48) | PUD)
-#define GPK12_DATA12	(GPK12 | FUNC(2))
-#define GPK12_GPIO	(GPK12 | FUNC(0))
-#define GPK13		(PIN(10,52) | PUD)
-#define GPK13_DATA13	(GPK13 | FUNC(2))
-#define GPK13_GPIO	(GPK13 | FUNC(0))
-#define GPK14		(PIN(10,56) | PUD)
-#define GPK14_DATA14	(GPK14 | FUNC(2))
-#define GPK14_GPIO	(GPK14 | FUNC(0))
-#define GPK15		(PIN(10,60) | PUD)
-#define GPK15_DATA15	(GPK15 | FUNC(2))
-#define GPK15_GPIO	(GPK15 | FUNC(0))
-
-#define GPL0		(PIN(11,0) | PUD)
-#define GPL0_ADDR0	(GPL0 | FUNC(2))
-#define GPL0_GPIO	(GPL0 | FUNC(0))
-#define GPL1		(PIN(11,4) | PUD)
-#define GPL1_ADDR1	(GPL1 | FUNC(2))
-#define GPL1_GPIO	(GPL1 | FUNC(0))
-#define GPL2		(PIN(11,8) | PUD)
-#define GPL2_ADDR2	(GPL2 | FUNC(2))
-#define GPL2_GPIO	(GPL2 | FUNC(0))
-#define GPL3		(PIN(11,12) | PUD)
-#define GPL3_ADDR3	(GPL3 | FUNC(2))
-#define GPL3_GPIO	(GPL3 | FUNC(0))
-#define GPL4		(PIN(11,16) | PUD)
-#define GPL4_ADDR3	(GPL4 | FUNC(2))
-#define GPL4_GPIO	(GPL4 | FUNC(0))
-#define GPL5		(PIN(11,20) | PUD)
-#define GPL5_ADDR3	(GPL5 | FUNC(2))
-#define GPL5_GPIO	(GPL5 | FUNC(0))
-#define GPL6		(PIN(11,24) | PUD)
-#define GPL6_ADDR3	(GPL6 | FUNC(2))
-#define GPL6_GPIO	(GPL6 | FUNC(0))
-#define GPL7		(PIN(11,28) | PUD)
-#define GPL7_ADDR3	(GPL7 | FUNC(2))
-#define GPL7_GPIO	(GPL7 | FUNC(0))
-#define GPL8		(PIN(11,32) | PUD)
-#define GPL8_ADDR3	(GPL8 | FUNC(2))
-#define GPL8_GPIO	(GPL8 | FUNC(0))
-#define GPL9		(PIN(11,36) | PUD)
-#define GPL9_ADDR3	(GPL9 | FUNC(2))
-#define GPL9_GPIO	(GPL9 | FUNC(0))
-#define GPL10		(PIN(11,40) | PUD)
-#define GPL10_ADDR3	(GPL10 | FUNC(2))
-#define GPL10_GPIO	(GPL10 | FUNC(0))
-#define GPL11		(PIN(11,44) | PUD)
-#define GPL11_ADDR3	(GPL11 | FUNC(2))
-#define GPL11_GPIO	(GPL11 | FUNC(0))
-#define GPL12		(PIN(11,48) | PUD)
-#define GPL12_ADDR3	(GPL12 | FUNC(2))
-#define GPL12_GPIO	(GPL12 | FUNC(0))
-#define GPL13		(PIN(11,52) | PUD)
-#define GPL13_ADDR16	(GPL13 | FUNC(2))
-#define GPL13_GPIO	(GPL13 | FUNC(0))
-#define GPL14		(PIN(11,65) | PUD)
-#define GPL14_ADDR17	(GPL14 | FUNC(2))
-#define GPL14_GPIO	(GPL14 | FUNC(0))
-
-#define GPM0		(PIN(12,0) | PUD)
-#define GPM0_GPIO	(GPM0 | FUNC(0))
-#define GPM1		(PIN(12,4) | PUD)
-#define GPM1_GPIO	(GPM1 | FUNC(0))
-#define GPM2		(PIN(12,8) | PUD)
-#define GPM2_GPIO	(GPM2 | FUNC(0))
-#define GPM3		(PIN(12,12) | PUD)
-#define GPM3_GPIO	(GPM3 | FUNC(0))
-#define GPM4		(PIN(12,16) | PUD)
-#define GPM4_GPIO	(GPM4 | FUNC(0))
-#define GPM5		(PIN(12,20) | PUD)
-#define GPM5_GPIO	(GPM5 | FUNC(0))
-
-#define GPN0		(PIN(13,0) | PUD)
-#define GPN0_GPIO	(GPN0 | FUNC(0))
-#define GPN1		(PIN(13,0) | PUD)
-#define GPN1_GPIO	(GPN1 | FUNC(0))
-#define GPN2		(PIN(13,0) | PUD)
-#define GPN2_GPIO	(GPN2 | FUNC(0))
-#define GPN3		(PIN(13,0) | PUD)
-#define GPN3_GPIO	(GPN3 | FUNC(0))
-#define GPN4		(PIN(13,0) | PUD)
-#define GPN4_GPIO	(GPN4 | FUNC(0))
-#define GPN5		(PIN(13,0) | PUD)
-#define GPN5_GPIO	(GPN5 | FUNC(0))
-#define GPN6		(PIN(13,0) | PUD)
-#define GPN6_GPIO	(GPN6 | FUNC(0))
-#define GPN7		(PIN(13,0) | PUD)
-#define GPN7_GPIO	(GPN7 | FUNC(0))
-#define GPN8		(PIN(13,0) | PUD)
-#define GPN8_GPIO	(GPN8 | FUNC(0))
-#define GPN9		(PIN(13,0) | PUD)
-#define GPN9_GPIO	(GPN9 | FUNC(0))
-#define GPN10		(PIN(13,20) | PUD)
-#define GPN10_GPIO	(GPN10 | FUNC(0))
-#define GPN11		(PIN(13,20) | PUD)
-#define GPN11_GPIO	(GPN11 | FUNC(0))
-#define GPN12		(PIN(13,20) | PUD)
-#define GPN12_GPIO	(GPN12 | FUNC(0))
-#define GPN13		(PIN(13,20) | PUD)
-#define GPN13_GPIO	(GPN13 | FUNC(0))
-#define GPN14		(PIN(13,20) | PUD)
-#define GPN14_GPIO	(GPN14 | FUNC(0))
-#define GPN15		(PIN(13,20) | PUD)
-#define GPN15_GPIO	(GPN15 | FUNC(0))
-
-#define GPO0		(PIN(14,0) | PUD)
-#define GPO0_GPIO	(GPO0 | FUNC(0))
-#define GPO0_NCS2	(GPO0 | FUNC(2))
-#define GPO1		(PIN(14,2) | PUD)
-#define GPO1_GPIO	(GPO1 | FUNC(0))
-#define GPO1_NCS3	(GPO1 | FUNC(2))
-#define GPO2		(PIN(14,4) | PUD)
-#define GPO2_GPIO	(GPO2 | FUNC(0))
-#define GPO2_NCS4	(GPO2 | FUNC(2))
-#define GPO3		(PIN(14,6) | PUD)
-#define GPO3_GPIO	(GPO3 | FUNC(0))
-#define GPO3_NCS5	(GPO3 | FUNC(2))
-#define GPO4		(PIN(14,8) | PUD)
-#define GPO4_GPIO	(GPO4 | FUNC(0))
-#define GPO5		(PIN(14,10) | PUD)
-#define GPO5_GPIO	(GPO5 | FUNC(0))
-#define GPO6		(PIN(14,12) | PUD)
-#define GPO6_GPIO	(GPO6 | FUNC(0))
-#define GPO6_ADDR6	(GPO6 | FUNC(2))
-#define GPO7		(PIN(14,14) | PUD)
-#define GPO7_GPIO	(GPO7 | FUNC(0))
-#define GPO7_ADDR7	(GPO7 | FUNC(2))
-#define GPO8		(PIN(14,16) | PUD)
-#define GPO8_GPIO	(GPO8 | FUNC(0))
-#define GPO8_ADDR8	(GPO8 | FUNC(2))
-#define GPO9		(PIN(14,18) | PUD)
-#define GPO9_GPIO	(GPO9 | FUNC(0))
-#define GPO9_ADDR9	(GPO9 | FUNC(2))
-#define GPO10		(PIN(14,20) | PUD)
-#define GPO10_GPIO	(GPO10 | FUNC(2))
-#define GPO10_ADDR10	(GPO10 | FUNC(2))
-#define GPO11		(PIN(14,22) | PUD)
-#define GPO11_GPIO	(GPO11 | FUNC(0))
-#define GPO11_ADDR11	(GPO11 | FUNC(2))
-#define GPO12		(PIN(14,24) | PUD)
-#define GPO12_GPIO	(GPO12 | FUNC(0))
-#define GPO12_ADDR12	(GPO12 | FUNC(2))
-#define GPO13		(PIN(14,26) | PUD)
-#define GPO13_GPIO	(GPO13 | FUNC(0))
-#define GPO13_ADDR13	(GPO13 | FUNC(2))
-#define GPO14		(PIN(14,28) | PUD)
-#define GPO14_GPIO	(GPO14 | FUNC(0))
-#define GPO14_ADDR14	(GPO14 | FUNC(2))
-#define GPO15		(PIN(14,30) | PUD)
-#define GPO15_GPIO	(GPO15 | FUNC(0))
-#define GPO15_ADDR15	(GPO15 | FUNC(2))
-
-#define GPP0		(PIN(15,0) | PUD)
-#define GPP0_GPIO	(GPP0 | FUNC(0))
-#define GPP1		(PIN(15,2) | PUD)
-#define GPP1_GPIO	(GPP1 | FUNC(0))
-#define GPP2		(PIN(15,4) | PUD)
-#define GPP2_NWAIT	(GPP2 | FUNC(2))
-#define GPP3		(PIN(15,6) | PUD)
-#define GPP3_FALE	(GPP3 | FUNC(2))
-#define GPP4		(PIN(15,8) | PUD)
-#define GPP4_FCLE	(GPP4 | FUNC(2))
-#define GPP5		(PIN(15,10) | PUD)
-#define GPP5_FWE	(GPP5 | FUNC(2))
-#define GPP6		(PIN(15,12) | PUD)
-#define GPP6_FRE	(GPP6 | FUNC(2))
-#define GPP7		(PIN(15,14) | PUD)
-#define GPP7_RNB	(GPP7 | FUNC(2))
-#define GPP8		(PIN(15,16) | PUD)
-#define GPP8_GPIO	(GPP8 | FUNC(0))
-#define GPP9		(PIN(15,18) | PUD)
-#define GPP9_GPIO	(GPP9 | FUNC(0))
-#define GPP10		(PIN(15,20) | PUD)
-#define GPP10_GPIO	(GPP10 | FUNC(0))
-#define GPP11		(PIN(15,22) | PUD)
-#define GPP11_GPIO	(GPP11 | FUNC(0))
-#define GPP12		(PIN(15,24) | PUD)
-#define GPP12_GPIO	(GPP12 | FUNC(0))
-#define GPP13		(PIN(15,26) | PUD)
-#define GPP13_GPIO	(GPP13 | FUNC(0))
-#define GPP14		(PIN(15,28) | PUD)
-#define GPP14_GPIO	(GPP14 | FUNC(0))
-
-#define GPQ0		(PIN(16,0) | PUD)
-#define GPQ0_GPIO	(GPQ0 | FUNC(0))
-#define GPQ1		(PIN(16,2) | PUD)
-#define GPQ1_GPIO	(GPQ1 | FUNC(0))
-#define GPQ2		(PIN(16,4) | PUD)
-#define GPQ2_GPIO	(GPQ2 | FUNC(0))
-#define GPQ3		(PIN(16,8) | PUD)
-#define GPQ3_GPIO	(GPQ3 | FUNC(0))
-#define GPQ4		(PIN(16,8) | PUD)
-#define GPQ4_GPIO	(GPQ4 | FUNC(0))
-#define GPQ5		(PIN(16,10) | PUD)
-#define GPQ5_GPIO	(GPQ5 | FUNC(0))
-#define GPQ6		(PIN(16,12) | PUD)
-#define GPQ6_GPIO	(GPQ6 | FUNC(0))
-#define GPQ7		(PIN(16,14) | PUD)
-#define GPQ7_GPIO	(GPQ7 | FUNC(0))
-#define GPQ8		(PIN(16,16) | PUD)
-#define GPQ8_GPIO	(GPQ7 | FUNC(0))
-
-
-#endif /* __MACH_IOMUX_S3C64XX_H */
diff --git a/arch/arm/mach-samsung/include/mach/iomux-s5pcxx.h b/arch/arm/mach-samsung/include/mach/iomux-s5pcxx.h
deleted file mode 100644
index 0677de46dd..0000000000
--- a/arch/arm/mach-samsung/include/mach/iomux-s5pcxx.h
+++ /dev/null
@@ -1,798 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- * Copyright (C) 2012 Alexey Galakhov
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Tested with S5PV210 */
-
-#ifndef __MACH_IOMUX_S5PCXX_H
-# define __MACH_IOMUX_S5PCXX_H
-
-/* 3322222222221111111111
- * 10987654321098765432109876543210
- *                           ^^^^^^_ Bit offset
- *                      ^^^^^_______ Group Number
- *                  ^^^^____________ Function
- *                 ^________________ initial GPIO out value
- *                ^_________________ Pull up/down feature present
- *              ^^__________________ initial pull up/down setting
- */
-
-#define PIN(group,bit) ((group << 6) + bit)
-#define FUNC(x) (((x) & 0xf) << 11)
-#define GET_FUNC(x) (((x) >> 11) & 0xf)
-#define GET_GROUP(x) (((x) >> 6) & 0x1f)
-#define GET_BIT(x) ((x) & 0x3f)
-#define GET_GPIOVAL(x) (!!((x) & (1 << 15)))
-#define GPIO_OUT (1 << 11)
-#define GPIO_IN (0 << 11)
-#define GPIO_VAL(x) ((!!(x)) << 15)
-#define PUD_MASK 0x3
-#define PUD (1 << 16)
-#define PUD_PRESENT(x) (!!((x) & (1 << 16)))
-#define DISABLE_PUD (0 << 17)
-#define ENABLE_PU (2 << 17)
-#define ENABLE_PD (1 << 17)
-#define GET_PUD(x) (((x) >> 17) & PUD_MASK)
-
-/*
- * To have a chance for simple GPIO manipulation routines
- * define the GPIO numbers with a real simple scheme.
- *
- * Keep in mind: The 'GPIO_2_NO' creates a value to be used with the real gpio
- * routines and *not* for the multiplexer routines!
- */
-#define GPIO_2_NO(x,y) (PIN(x,y))
-
-/*
- * Group A0: GPIO 0...7
- * Used GPIO: 0...7
- * These pins can also act as GPIO outputs
- */
-#define GPA00		(PIN(0,0) | PUD)
-#define GPA00_GPIO	(GPA00 | FUNC(0))
-#define GPA00_RXD0	(GPA00 | FUNC(2))
-#define GPA01		(PIN(0,1) | PUD)
-#define GPA01_GPIO	(GPA01 | FUNC(0))
-#define GPA01_TXD0	(GPA01 | FUNC(2))
-#define GPA02		(PIN(0,2) | PUD)
-#define GPA02_GPIO	(GPA02 | FUNC(0))
-#define GPA02_NCTS0	(GPA02 | FUNC(2))
-#define GPA03		(PIN(0,3) | PUD)
-#define GPA03_GPIO	(GPA03 | FUNC(0))
-#define GPA03_NRTS0	(GPA03 | FUNC(2))
-#define GPA04		(PIN(0,4) | PUD)
-#define GPA04_GPIO	(GPA04 | FUNC(0))
-#define GPA04_RXD1	(GPA04 | FUNC(2))
-#define GPA05		(PIN(0,5) | PUD)
-#define GPA05_GPIO	(GPA05 | FUNC(0))
-#define GPA05_TXD1	(GPA05 | FUNC(2))
-#define GPA06		(PIN(0,6) | PUD)
-#define GPA06_GPIO	(GPA06 | FUNC(0))
-#define GPA06_NCTS1	(GPA06 | FUNC(2))
-#define GPA07		(PIN(0,7) | PUD)
-#define GPA07_GPIO	(GPA07 | FUNC(0))
-#define GPA07_NRTS1	(GPA07 | FUNC(2))
-
-/*
- * Group A1: GPIO 0..3
- * Used GPIO: 0..3
- * These pins can also act as GPIO outputs
- */
-#define GPA10		(PIN(1,0) | PUD)
-#define GPA10_GPIO	(GPA10 | FUNC(0))
-#define GPA10_RXD2	(GPA10 | FUNC(2))
-#define GPA10_RXDAUD	(GPA0 | FUNC(4))
-#define GPA11		(PIN(1,1) | PUD)
-#define GPA11_GPIO	(GPA11 | FUNC(0))
-#define GPA11_TXD2	(GPA11 | FUNC(2))
-#define GPA11_TXDAUD	(GPA1 | FUNC(4))
-#define GPA12		(PIN(1,2) | PUD)
-#define GPA12_GPIO	(GPA12 | FUNC(0))
-#define GPA12_RXD3	(GPA12 | FUNC(2))
-#define GPA12_NCTS2	(GPA12 | FUNC(3))
-#define GPA13		(PIN(1,3) | PUD)
-#define GPA13_GPIO	(GPA13 | FUNC(0))
-#define GPA13_TXD3	(GPA13 | FUNC(2))
-#define GPA13_NRTS2	(GPA13 | FUNC(3))
-
-
-/*
- * Group B: GPIO 0...7
- * Used GPIO: 0...7
- * These pins can also act as GPIO outputs
- */
-#define GPB0		(PIN(2,0) | PUD)
-#define GPB0_GPIO	(GPB0 | FUNC(0))
-#define GPB0_SPI0_CLK   (GPB0 | FUNC(2))
-#define GPB1		(PIN(2,1) | PUD)
-#define GPB1_GPIO	(GPB1 | FUNC(0))
-#define GPB1_SPI0_NCS	(GPB1 | FUNC(2))
-#define GPB2		(PIN(2,2) | PUD)
-#define GPB2_GPIO	(GPB2 | FUNC(0))
-#define GPB2_SPI0_MISO	(GPB2 | FUNC(2))
-#define GPB3		(PIN(2,3) | PUD)
-#define GPB3_GPIO	(GPB3 | FUNC(0))
-#define GPB3_SPI0_MOSI	(GPB3 | FUNC(2))
-#define GPB4		(PIN(2,4) | PUD)
-#define GPB4_GPIO	(GPB4 | FUNC(0))
-#define GPB4_SPI1_CLK	(GPB4 | FUNC(2))
-#define GPB5		(PIN(2,5) | PUD)
-#define GPB5_GPIO	(GPB5 | FUNC(0))
-#define GPB5_SPI1_NCS	(GPB5 | FUNC(0))
-#define GPB6		(PIN(2,6) | PUD)
-#define GPB6_GPIO	(GPB6 | FUNC(0))
-#define GPB6_SPI1_MISO	(GPB6 | FUNC(0))
-#define GPB7		(PIN(2,7) | PUD)
-#define GPB7_GPIO	(GPB7 | FUNC(0))
-#define GPB7_SPI1_MOSI	(GPB7 | FUNC(0))
-
-/*
- * Group C0: GPIO 0...4
- */
-#define GPC00			(PIN(3,0) | PUD)
-#define GPC00_GPIO		(GPC00 | FUNC(0))
-#define GPC00_I2S1_SCLK		(GPC00 | FUNC(2))
-#define GPC00_PCM1_SCLK		(GPC00 | FUNC(3))
-#define GPC00_AC97_BITCLK	(GPC00 | FUNC(4))
-#define GPC01			(PIN(3,1) | PUD)
-#define GPC01_GPIO		(GPC01 | FUNC(0))
-#define GPC01_I2S1_CDCLK	(GPC01 | FUNC(2))
-#define GPC01_PCM1_EXTCLK	(GPC01 | FUNC(3))
-#define GPC01_AC97_NRESET	(GPC01 | FUNC(4))
-#define GPC02			(PIN(3,2) | PUD)
-#define GPC02_GPIO		(GPC02 | FUNC(0))
-#define GPC02_I2S1_LRCK		(GPC02 | FUNC(2))
-#define GPC02_PCM1_FSYNC	(GPC02 | FUNC(3))
-#define GPC02_AC97_SYNC		(GPC02 | FUNC(4))
-#define GPC03			(PIN(3,3) | PUD)
-#define GPC03_GPIO		(GPC03 | FUNC(0))
-#define GPC03_I2S1_SDI		(GPC03 | FUNC(2))
-#define GPC03_PCM1_SIN		(GPC03 | FUNC(3))
-#define GPC03_AC97_SDI		(GPC03 | FUNC(4))
-#define GPC04			(PIN(3,4) | PUD)
-#define GPC04_GPIO		(GPC04 | FUNC(0))
-#define GPC04_I2S1_SDO		(GPC04 | FUNC(2))
-#define GPC04_PCM1_SOUT		(GPC04 | FUNC(3))
-#define GPC04_AC97_SDO		(GPC04 | FUNC(4))
-
-/*
- * Group C1: GPIO 0...4
- */
-#define GPC10			(PIN(4,0) | PUD)
-#define GPC10_GPIO		(GPC10 | FUNC(0))
-#define GPC10_PCM2_SCLK		(GPC10 | FUNC(2))
-#define GPC10_SPDIF_0_OUT	(GPC10 | FUNC(3))
-#define GPC10_I2S2_SCLK		(GPC10 | FUNC(4))
-#define GPC11			(PIN(4,1) | PUD)
-#define GPC11_GPIO		(GPC11 | FUNC(0))
-#define GPC11_PCM2_EXTCLK	(GPC11 | FUNC(2))
-#define GPC11_SPDIF_EXTCLK	(GPC11 | FUNC(3))
-#define GPC11_I2S2_CDCLK	(GPC11 | FUNC(4))
-#define GPC12			(PIN(4,2) | PUD)
-#define GPC12_GPIO		(GPC12 | FUNC(0))
-#define GPC12_PCM2_FSYNC	(GPC12 | FUNC(2))
-#define GPC12_LCD_FRM		(GPC12 | FUNC(3))
-#define GPC12_I2S2_LRCK		(GPC12 | FUNC(4))
-#define GPC13			(PIN(4,3) | PUD)
-#define GPC13_GPIO		(GPC13 | FUNC(0))
-#define GPC13_PCM2_SIN		(GPC13 | FUNC(2))
-#define GPC13_I2S2_SDI		(GPC13 | FUNC(4))
-#define GPC14			(PIN(4,4) | PUD)
-#define GPC14_GPIO		(GPC14 | FUNC(0))
-#define GPC14_PCM2_SOUT		(GPC14 | FUNC(2))
-#define GPC14_I2S2_SDO		(GPC14 | FUNC(4))
-
-/*
- * Group D0: GPIO 0...3
- */
-#define GPD00		(PIN(5,0) | PUD)
-#define GPD00_GPIO	(GPD00 | FUNC(0))
-#define GPD00_TOUT_0	(GPD00 | FUNC(2))
-#define GPD01		(PIN(5,1) | PUD)
-#define GPD01_GPIO	(GPD01 | FUNC(0))
-#define GPD01_TOUT_1	(GPD01 | FUNC(2))
-#define GPD02		(PIN(5,2) | PUD)
-#define GPD02_GPIO	(GPD02 | FUNC(0))
-#define GPD02_TOUT_2	(GPD02 | FUNC(2))
-#define GPD03		(PIN(5,3) | PUD)
-#define GPD03_GPIO	(GPD03 | FUNC(0))
-#define GPD03_TOUT_3	(GPD03 | FUNC(2))
-
-/*
- * Group D1: GPIO 0...5
- */
-#define GPD10		(PIN(6,0) | PUD)
-#define GPD10_GPIO	(GPD10 | FUNC(0))
-#define GPD10_I2C0_SDA	(GPD10 | FUNC(2))
-#define GPD11		(PIN(6,0) | PUD)
-#define GPD11_GPIO	(GPD11 | FUNC(0))
-#define GPD11_I2C0_SCL	(GPD11 | FUNC(2))
-#define GPD12		(PIN(6,0) | PUD)
-#define GPD12_GPIO	(GPD12 | FUNC(0))
-#define GPD12_I2C1_SDA	(GPD12 | FUNC(2))
-#define GPD13		(PIN(6,0) | PUD)
-#define GPD13_GPIO	(GPD13 | FUNC(0))
-#define GPD13_I2C1_SCL	(GPD13 | FUNC(2))
-#define GPD14		(PIN(6,0) | PUD)
-#define GPD14_GPIO	(GPD14 | FUNC(0))
-#define GPD14_I2C2_SDA	(GPD14 | FUNC(2))
-#define GPD15		(PIN(6,0) | PUD)
-#define GPD15_GPIO	(GPD15 | FUNC(0))
-#define GPD15_I2C2_SCL	(GPD15 | FUNC(2))
-
-/*
- * Group E0: GPIO 0...7
- */
-#define GPE00			(PIN(7,0) | PUD)
-#define GPE00_GPIO		(GPE00 | FUNC(0))
-#define GPE00_CAM_A_PCLK	(GPE00 | FUNC(2))
-#define GPE01			(PIN(7,1) | PUD)
-#define GPE01_GPIO		(GPE01 | FUNC(0))
-#define GPE01_CAM_A_VSYNC	(GPE01 | FUNC(2))
-#define GPE02			(PIN(7,2) | PUD)
-#define GPE02_GPIO		(GPE02 | FUNC(0))
-#define GPE02_CAM_A_HREF	(GPE02 | FUNC(2))
-#define GPE03			(PIN(7,3) | PUD)
-#define GPE03_GPIO		(GPE03 | FUNC(0))
-#define GPE03_CAM_A_DATA0	(GPE03 | FUNC(2))
-#define GPE04			(PIN(7,4) | PUD)
-#define GPE04_GPIO		(GPE04 | FUNC(0))
-#define GPE04_CAM_A_DATA1	(GPE04 | FUNC(2))
-#define GPE05			(PIN(7,5) | PUD)
-#define GPE05_GPIO		(GPE05 | FUNC(0))
-#define GPE05_CAM_A_DATA2	(GPE05 | FUNC(2))
-#define GPE06			(PIN(7,6) | PUD)
-#define GPE06_GPIO		(GPE06 | FUNC(0))
-#define GPE06_CAM_A_DATA3	(GPE06 | FUNC(2))
-#define GPE07			(PIN(7,7) | PUD)
-#define GPE07_GPIO		(GPE07 | FUNC(0))
-#define GPE07_CAM_A_DATA4	(GPE07 | FUNC(2))
-
-/*
- * Group E1: GPIO 0...4
- */
-#define GPE10			(PIN(8,0) | PUD)
-#define GPE10_GPIO		(GPE10 | FUNC(0))
-#define GPE10_CAM_A_DATA5	(GPE10 | FUNC(2))
-#define GPE11			(PIN(8,1) | PUD)
-#define GPE11_GPIO		(GPE11 | FUNC(0))
-#define GPE11_CAM_A_DATA6	(GPE11 | FUNC(2))
-#define GPE12			(PIN(8,2) | PUD)
-#define GPE12_GPIO		(GPE12 | FUNC(0))
-#define GPE12_CAM_A_DATA7	(GPE12 | FUNC(2))
-#define GPE13			(PIN(8,3) | PUD)
-#define GPE13_GPIO		(GPE13 | FUNC(0))
-#define GPE13_CAM_A_CLKOUT	(GPE13 | FUNC(2))
-#define GPE14			(PIN(8,4) | PUD)
-#define GPE14_GPIO		(GPE14 | FUNC(0))
-#define GPE14_CAM_A_FIELD	(GPE14 | FUNC(2))
-
-/*
- * Group F0: GPIO 0...7
- */
-#define GPF00		(PIN(9,0) | PUD)
-#define GPF00_GPIO	(GPF00 | FUNC(0))
-#define GPF00_LCD_HSYNC	(GPF00 | FUNC(2))
-#define GPF00_SYS_CS0	(GPF00 | FUNC(3))
-#define GPF00_VEN_HSYNC	(GPF00 | FUNC(4))
-#define GPF01		(PIN(9,1) | PUD)
-#define GPF01_GPIO	(GPF01 | FUNC(0))
-#define GPF01_LCD_VSYNC	(GPF01 | FUNC(2))
-#define GPF01_SYS_CS1	(GPF01 | FUNC(3))
-#define GPF01_VEN_VSYNC	(GPF01 | FUNC(4))
-#define GPF02		(PIN(9,2) | PUD)
-#define GPF02_GPIO	(GPF02 | FUNC(0))
-#define GPF02_LCD_VDEN	(GPF02 | FUNC(2))
-#define GPF02_SYS_RS	(GPF02 | FUNC(3))
-#define GPF02_VEN_HREF	(GPF02 | FUNC(4))
-#define GPF03		(PIN(9,3) | PUD)
-#define GPF03_GPIO	(GPF03 | FUNC(0))
-#define GPF03_LCD_VCLK	(GPF03 | FUNC(2))
-#define GPF03_SYS_WE	(GPF03 | FUNC(3))
-#define GPF03_V601_CLK	(GPF03 | FUNC(4))
-#define GPF04		(PIN(9,4) | PUD)
-#define GPF04_GPIO	(GPF04 | FUNC(0))
-#define GPF04_LCD_VD0	(GPF04 | FUNC(2))
-#define GPF04_SYS_VS0	(GPF04 | FUNC(3))
-#define GPF04_VEN_DATA0	(GPF04 | FUNC(4))
-#define GPF05		(PIN(9,5) | PUD)
-#define GPF05_GPIO	(GPF05 | FUNC(0))
-#define GPF05_LCD_VD1	(GPF05 | FUNC(2))
-#define GPF05_SYS_VD1	(GPF05 | FUNC(3))
-#define GPF05_VEN_DATA1	(GPF05 | FUNC(4))
-#define GPF06		(PIN(9,6) | PUD)
-#define GPF06_GPIO	(GPF06 | FUNC(0))
-#define GPF06_LCD_VD2	(GPF06 | FUNC(2))
-#define GPF06_SYS_VD2	(GPF06 | FUNC(3))
-#define GPF06_VEN_DATA2	(GPF06 | FUNC(4))
-#define GPF07		(PIN(9,7) | PUD)
-#define GPF07_GPIO	(GPF07 | FUNC(0))
-#define GPF07_LCD_VD3	(GPF07 | FUNC(2))
-#define GPF07_SYS_VD3	(GPF07 | FUNC(3))
-#define GPF07_VEN_DATA3	(GPF07 | FUNC(4))
-
-/*
- * Group F1: GPIO 0...7
- */
-#define GPF10			(PIN(10,0) | PUD)
-#define GPF10_GPIO		(GPF10 | FUNC(0))
-#define GPF10_LCD_VD4		(GPF10 | FUNC(2))
-#define GPF10_SYS_VD4		(GPF10 | FUNC(3))
-#define GPF10_VEN_DATA4		(GPF10 | FUNC(4))
-#define GPF11			(PIN(10,1) | PUD)
-#define GPF11_GPIO		(GPF11 | FUNC(0))
-#define GPF11_LCD_VD5		(GPF11 | FUNC(2))
-#define GPF11_SYS_VD5		(GPF11 | FUNC(3))
-#define GPF11_VEN_DATA5		(GPF11 | FUNC(4))
-#define GPF12			(PIN(10,2) | PUD)
-#define GPF12_GPIO		(GPF12 | FUNC(0))
-#define GPF12_LCD_VD6		(GPF12 | FUNC(2))
-#define GPF12_SYS_VD6		(GPF12 | FUNC(3))
-#define GPF12_VEN_DATA6		(GPF12 | FUNC(4))
-#define GPF13			(PIN(10,3) | PUD)
-#define GPF13_GPIO		(GPF13 | FUNC(0))
-#define GPF13_LCD_VD7		(GPF13 | FUNC(2))
-#define GPF13_SYS_VD7		(GPF13 | FUNC(3))
-#define GPF13_VEN_DATA7		(GPF13 | FUNC(4))
-#define GPF14			(PIN(10,4) | PUD)
-#define GPF14_GPIO		(GPF14 | FUNC(0))
-#define GPF14_LCD_VD8		(GPF14 | FUNC(2))
-#define GPF14_SYS_VD8		(GPF14 | FUNC(3))
-#define GPF14_V656_DATA0	(GPF14 | FUNC(4))
-#define GPF15			(PIN(10,5) | PUD)
-#define GPF15_GPIO		(GPF15 | FUNC(0))
-#define GPF15_LCD_VD9		(GPF15 | FUNC(2))
-#define GPF15_SYS_VD9		(GPF15 | FUNC(3))
-#define GPF15_V656_DATA1	(GPF15 | FUNC(4))
-#define GPF16			(PIN(10,6) | PUD)
-#define GPF16_GPIO		(GPF16 | FUNC(0))
-#define GPF16_LCD_VD10		(GPF16 | FUNC(2))
-#define GPF16_SYS_VD10		(GPF16 | FUNC(3))
-#define GPF16_V656_DATA2	(GPF16 | FUNC(4))
-#define GPF17			(PIN(10,7) | PUD)
-#define GPF17_GPIO		(GPF17 | FUNC(0))
-#define GPF17_LCD_VD11		(GPF17 | FUNC(2))
-#define GPF17_SYS_VD11		(GPF17 | FUNC(3))
-#define GPF17_V656_DATA3	(GPF17 | FUNC(4))
-
-/*
- * Group F2: GPIO 0...7
- */
-#define GPF20			(PIN(11,0) | PUD)
-#define GPF20_GPIO		(GPF20 | FUNC(0))
-#define GPF20_LCD_VD_12		(GPF20 | FUNC(2))
-#define GPF20_SYS_VD_12		(GPF20 | FUNC(3))
-#define GPF20_V656_DATA_4	(GPF20 | FUNC(4))
-#define GPF21			(PIN(11,1) | PUD)
-#define GPF21_GPIO		(GPF21 | FUNC(0))
-#define GPF21_LCD_VD_13		(GPF21 | FUNC(2))
-#define GPF21_SYS_VD_13		(GPF21 | FUNC(3))
-#define GPF21_V656_DATA_5	(GPF21 | FUNC(4))
-#define GPF22			(PIN(11,2) | PUD)
-#define GPF22_GPIO		(GPF22 | FUNC(0))
-#define GPF22_LCD_VD_14		(GPF22 | FUNC(2))
-#define GPF22_SYS_VD_14		(GPF22 | FUNC(3))
-#define GPF22_V656_DATA_6	(GPF22 | FUNC(4))
-#define GPF23			(PIN(11,3) | PUD)
-#define GPF23_GPIO		(GPF23 | FUNC(0))
-#define GPF23_LCD_VD_15		(GPF23 | FUNC(2))
-#define GPF23_SYS_VD_15		(GPF23 | FUNC(3))
-#define GPF23_V656_DATA_7	(GPF23 | FUNC(4))
-#define GPF24			(PIN(11,4) | PUD)
-#define GPF24_GPIO		(GPF24 | FUNC(0))
-#define GPF24_LCD_VD_16		(GPF24 | FUNC(2))
-#define GPF24_SYS_VD_16		(GPF24 | FUNC(3))
-#define GPF25			(PIN(11,5) | PUD)
-#define GPF25_GPIO		(GPF25 | FUNC(0))
-#define GPF25_LCD_VD_17		(GPF25 | FUNC(2))
-#define GPF25_SYS_VD_17		(GPF25 | FUNC(3))
-#define GPF26			(PIN(11,6) | PUD)
-#define GPF26_GPIO		(GPF26 | FUNC(0))
-#define GPF26_LCD_VD_18		(GPF26 | FUNC(2))
-#define GPF26_SYS_VD_18		(GPF26 | FUNC(3))
-#define GPF27			(PIN(11,7) | PUD)
-#define GPF27_GPIO		(GPF27 | FUNC(0))
-#define GPF27_LCD_VD_19		(GPF27 | FUNC(2))
-#define GPF27_SYS_VD_19		(GPF27 | FUNC(3))
-
-/*
- * Group F3: GPIO 0...5
- */
-#define GPF30		(PIN(12,0) | PUD)
-#define GPF30_GPIO	(GPF30 | FUNC(0))
-#define GPF30_LCD_VD20	(GPF30 | FUNC(2))
-#define GPF30_SYS_VD20	(GPF30 | FUNC(3))
-#define GPF31		(PIN(12,1) | PUD)
-#define GPF31_GPIO	(GPF31 | FUNC(0))
-#define GPF31_LCD_VD21	(GPF31 | FUNC(2))
-#define GPF31_SYS_VD21	(GPF31 | FUNC(3))
-#define GPF32		(PIN(12,2) | PUD)
-#define GPF32_GPIO	(GPF32 | FUNC(0))
-#define GPF32_LCD_VD22	(GPF32 | FUNC(2))
-#define GPF32_SYS_VD22	(GPF32 | FUNC(3))
-#define GPF33		(PIN(12,3) | PUD)
-#define GPF33_GPIO	(GPF33 | FUNC(0))
-#define GPF33_LCD_VD23	(GPF33 | FUNC(2))
-#define GPF33_SYS_VD23	(GPF33 | FUNC(3))
-#define GPF33_V656_CLK	(GPF33 | FUNC(4))
-#define GPF34		(PIN(12,4) | PUD)
-#define GPF34_GPIO	(GPF34 | FUNC(0))
-#define GPF34_VSYNC_LDI	(GPF34 | FUNC(3))
-#define GPF35		(PIN(12,5) | PUD)
-#define GPF35_GPIO	(GPF35 | FUNC(0))
-#define GPF35_SYS_OE	(GPF35 | FUNC(3))
-#define GPF35_VEN_FIELD	(GPF35 | FUNC(4))
-
-/*
- * Group G0: GPIO 0...6
- */
-#define GPG00		(PIN(13,0) | PUD)
-#define GPG00_GPIO	(GPG00 | FUNC(0))
-#define GPG00_SD0_CLK	(GPG00 | FUNC(2))
-#define GPG01		(PIN(13,1) | PUD)
-#define GPG01_GPIO	(GPG01 | FUNC(0))
-#define GPG01_SD0_CMD	(GPG01 | FUNC(2))
-#define GPG02		(PIN(13,2) | PUD)
-#define GPG02_GPIO	(GPG02 | FUNC(0))
-#define GPG02_SD0_NCD	(GPG02 | FUNC(2))
-#define GPG03		(PIN(13,3) | PUD)
-#define GPG03_GPIO	(GPG03 | FUNC(0))
-#define GPG03_SD0_DATA0	(GPG03 | FUNC(2))
-#define GPG04		(PIN(13,4) | PUD)
-#define GPG04_GPIO	(GPG04 | FUNC(0))
-#define GPG04_SD0_DATA1	(GPG04 | FUNC(2))
-#define GPG05		(PIN(13,5) | PUD)
-#define GPG05_GPIO	(GPG05 | FUNC(0))
-#define GPG05_SD0_DATA2	(GPG05 | FUNC(2))
-#define GPG06		(PIN(13,6) | PUD)
-#define GPG06_GPIO	(GPG06 | FUNC(0))
-#define GPG06_SD0_DATA3	(GPG06 | FUNC(2))
-
-/*
- * Group G1: GPIO 0...6
- */
-#define GPG10		(PIN(14,0) | PUD)
-#define GPG10_GPIO	(GPG10 | FUNC(0))
-#define GPG10_SD1_CLK	(GPG10 | FUNC(2))
-#define GPG11		(PIN(14,1) | PUD)
-#define GPG11_GPIO	(GPG11 | FUNC(0))
-#define GPG11_SD1_CMD	(GPG11 | FUNC(2))
-#define GPG12		(PIN(14,2) | PUD)
-#define GPG12_GPIO	(GPG12 | FUNC(0))
-#define GPG12_SD1_NCD	(GPG12 | FUNC(2))
-#define GPG13		(PIN(14,3) | PUD)
-#define GPG13_GPIO	(GPG13 | FUNC(0))
-#define GPG13_SD1_DATA0	(GPG13 | FUNC(2))
-#define GPG13_SD0_DATA4	(GPG13 | FUNC(3))
-#define GPG14		(PIN(14,4) | PUD)
-#define GPG14_GPIO	(GPG14 | FUNC(0))
-#define GPG14_SD1_DATA1	(GPG14 | FUNC(2))
-#define GPG14_SD0_DATA5	(GPG14 | FUNC(3))
-#define GPG15		(PIN(14,5) | PUD)
-#define GPG15_GPIO	(GPG15 | FUNC(0))
-#define GPG15_SD1_DATA2	(GPG15 | FUNC(2))
-#define GPG15_SD0_DATA6	(GPG15 | FUNC(3))
-#define GPG16		(PIN(14,6) | PUD)
-#define GPG16_GPIO	(GPG16 | FUNC(0))
-#define GPG16_SD1_DATA3	(GPG16 | FUNC(2))
-#define GPG16_SD0_DATA7	(GPG16 | FUNC(3))
-
-/*
- * Group G2: GPIO 0...6
- */
-#define GPG20		(PIN(15,0) | PUD)
-#define GPG20_GPIO	(GPG20 | FUNC(0))
-#define GPG20_SD2_CLK	(GPG20 | FUNC(2))
-#define GPG21		(PIN(15,1) | PUD)
-#define GPG21_GPIO	(GPG21 | FUNC(0))
-#define GPG21_SD2_CMD	(GPG21 | FUNC(2))
-#define GPG22		(PIN(15,2) | PUD)
-#define GPG22_GPIO	(GPG22 | FUNC(0))
-#define GPG22_SD2_NCD	(GPG22 | FUNC(2))
-#define GPG23		(PIN(15,3) | PUD)
-#define GPG23_GPIO	(GPG23 | FUNC(0))
-#define GPG23_SD2_DATA0	(GPG23 | FUNC(2))
-#define GPG24		(PIN(15,4) | PUD)
-#define GPG24_GPIO	(GPG24 | FUNC(0))
-#define GPG24_SD2_DATA1	(GPG24 | FUNC(2))
-#define GPG25		(PIN(15,5) | PUD)
-#define GPG25_GPIO	(GPG25 | FUNC(0))
-#define GPG25_SD2_DATA2	(GPG25 | FUNC(2))
-#define GPG26		(PIN(15,6) | PUD)
-#define GPG26_GPIO	(GPG26 | FUNC(0))
-#define GPG26_SD2_DATA3	(GPG26 | FUNC(2))
-
-/*
- * Group G3: GPIO 0...6
- */
-#define GPG30		(PIN(16,0) | PUD)
-#define GPG30_GPIO	(GPG30 | FUNC(0))
-#define GPG30_SD3_CLK	(GPG30 | FUNC(2))
-#define GPG31		(PIN(16,1) | PUD)
-#define GPG31_GPIO	(GPG31 | FUNC(0))
-#define GPG31_SD3_CMD	(GPG31 | FUNC(2))
-#define GPG32		(PIN(16,2) | PUD)
-#define GPG32_GPIO	(GPG32 | FUNC(0))
-#define GPG32_SD3_NCD	(GPG32 | FUNC(2))
-#define GPG33		(PIN(16,3) | PUD)
-#define GPG33_GPIO	(GPG33 | FUNC(0))
-#define GPG33_SD3_DATA0	(GPG33 | FUNC(2))
-#define GPG33_SD2_DATA4	(GPG33 | FUNC(3))
-#define GPG34		(PIN(16,4) | PUD)
-#define GPG34_GPIO	(GPG34 | FUNC(0))
-#define GPG34_SD3_DATA1	(GPG34 | FUNC(2))
-#define GPG34_SD2_DATA5	(GPG34 | FUNC(3))
-#define GPG35		(PIN(16,5) | PUD)
-#define GPG35_GPIO	(GPG35 | FUNC(0))
-#define GPG35_SD3_DATA2	(GPG35 | FUNC(2))
-#define GPG35_SD2_DATA6	(GPG35 | FUNC(3))
-#define GPG36		(PIN(16,6) | PUD)
-#define GPG36_GPIO	(GPG36 | FUNC(0))
-#define GPG36_SD3_DATA3	(GPG36 | FUNC(2))
-#define GPG36_SD2_DATA7	(GPG36 | FUNC(3))
-
-/*
- * Group I - no GPIO
- */
-#define GPI0			(PIN(17,0) | PUD)
-#define GPI0_I2S0_SCLK		(GPI0 | FUNC(2))
-#define GPI0_PCM0_SCLK		(GPI0 | FUNC(3))
-#define GPI1			(PIN(17,1) | PUD)
-#define GPI1_I2S0_CDCLK		(GPI1 | FUNC(2))
-#define GPI1_PCM0_EXTCLK	(GPI1 | FUNC(3))
-#define GPI2			(PIN(17,2) | PUD)
-#define GPI2_I2S0_LRCK		(GPI2 | FUNC(2))
-#define GPI2_PCM0_FSYNC		(GPI2 | FUNC(3))
-#define GPI3			(PIN(17,3) | PUD)
-#define GPI3_I2S0_SDI		(GPI3 | FUNC(2))
-#define GPI3_PCM0_SIN		(GPI3 | FUNC(3))
-#define GPI4			(PIN(17,4) | PUD)
-#define GPI4_I2S0_SDO0		(GPI4 | FUNC(2))
-#define GPI4_PCM0_SOUT		(GPI4 | FUNC(3))
-#define GPI5			(PIN(17,5) | PUD)
-#define GPI5_I2S0_SDO1		(GPI5 | FUNC(2))
-#define GPI6			(PIN(17,6) | PUD)
-#define GPI6_I2S0_SDO2		(GPI6 | FUNC(2))
-
-/*
- * Group J0: GPIO 0...7
- */
-#define GPJ00			(PIN(18,0) | PUD)
-#define GPJ00_GPIO		(GPJ00 | FUNC(0))
-#define GPJ00_MSM_ADDR0		(GPJ00 | FUNC(2))
-#define GPJ00_CAM_B_DATA0	(GPJ00 | FUNC(3))
-#define GPJ00_CF_ADDR0		(GPJ00 | FUNC(4))
-#define GPJ00_MIPI_BYTE_CLK	(GPJ00 | FUNC(5))
-#define GPJ01			(PIN(18,1) | PUD)
-#define GPJ01_GPIO		(GPJ01 | FUNC(0))
-#define GPJ01_MSM_ADDR1		(GPJ01 | FUNC(2))
-#define GPJ01_CAM_B_DATA1	(GPJ01 | FUNC(3))
-#define GPJ01_CF_ADDR1		(GPJ01 | FUNC(4))
-#define GPJ01_MIPI_ESC_CLK	(GPJ01 | FUNC(5))
-#define GPJ02			(PIN(18,2) | PUD)
-#define GPJ02_GPIO		(GPJ02 | FUNC(0))
-#define GPJ02_MSM_ADDR2		(GPJ02 | FUNC(2))
-#define GPJ02_CAM_B_DATA2	(GPJ02 | FUNC(3))
-#define GPJ02_CF_ADDR2		(GPJ02 | FUNC(4))
-#define GPJ02_TS_CLK		(GPJ02 | FUNC(5))
-#define GPJ03			(PIN(18,3) | PUD)
-#define GPJ03_GPIO		(GPJ03 | FUNC(0))
-#define GPJ03_MSM_ADDR3		(GPJ03 | FUNC(2))
-#define GPJ03_CAM_B_DATA3	(GPJ03 | FUNC(3))
-#define GPJ03_CF_IORDY		(GPJ03 | FUNC(4))
-#define GPJ03_TS_SYNC		(GPJ03 | FUNC(5))
-#define GPJ04			(PIN(18,4) | PUD)
-#define GPJ04_GPIO		(GPJ04 | FUNC(0))
-#define GPJ04_MSM_ADDR4		(GPJ04 | FUNC(2))
-#define GPJ04_CAM_B_DATA4	(GPJ04 | FUNC(3))
-#define GPJ04_CF_INTRQ		(GPJ04 | FUNC(4))
-#define GPJ04_TS_VAL		(GPJ04 | FUNC(5))
-#define GPJ05			(PIN(18,5) | PUD)
-#define GPJ05_GPIO		(GPJ05 | FUNC(0))
-#define GPJ05_MSM_ADDR5		(GPJ05 | FUNC(2))
-#define GPJ05_CAM_B_DATA5	(GPJ05 | FUNC(3))
-#define GPJ05_CF_DMARQ		(GPJ05 | FUNC(4))
-#define GPJ05_TS_DATA		(GPJ05 | FUNC(5))
-#define GPJ06			(PIN(18,6) | PUD)
-#define GPJ06_GPIO		(GPJ06 | FUNC(0))
-#define GPJ06_MSM_ADDR6		(GPJ06 | FUNC(2))
-#define GPJ06_CAM_B_DATA6	(GPJ06 | FUNC(3))
-#define GPJ06_CF_NDRESET	(GPJ06 | FUNC(4))
-#define GPJ06_TS_ERROR		(GPJ06 | FUNC(5))
-#define GPJ07			(PIN(18,7) | PUD)
-#define GPJ07_GPIO		(GPJ07 | FUNC(0))
-#define GPJ07_MSM_ADDR7		(GPJ07 | FUNC(2))
-#define GPJ07_CAM_B_DATA7	(GPJ07 | FUNC(3))
-#define GPJ07_CF_NDMACK		(GPJ07 | FUNC(4))
-#define GPJ07_MHL_D0		(GPJ07 | FUNC(5))
-
-/*
- * Group J1: GPIO 0...5
- */
-#define GPJ10			(PIN(19,0) | PUD)
-#define GPJ10_GPIO		(GPJ10 | FUNC(0))
-#define GPJ10_MSM_ADDR8		(GPJ10 | FUNC(2))
-#define GPJ10_CAM_B_PCLK	(GPJ10 | FUNC(3))
-#define GPJ10_SROM_ADDR_16to220	(GPJ10 | FUNC(4))
-#define GPJ10_MHL_D1		(GPJ10 | FUNC(5))
-#define GPJ11			(PIN(19,1) | PUD)
-#define GPJ11_GPIO		(GPJ11 | FUNC(0))
-#define GPJ11_MSM_ADDR9		(GPJ11 | FUNC(2))
-#define GPJ11_CAM_B_VSYNC	(GPJ11 | FUNC(3))
-#define GPJ11_SROM_ADDR_16to221	(GPJ11 | FUNC(4))
-#define GPJ11_MHL_D2		(GPJ11 | FUNC(5))
-#define GPJ12			(PIN(19,2) | PUD)
-#define GPJ12_GPIO		(GPJ12 | FUNC(0))
-#define GPJ12_MSM_ADDR10	(GPJ12 | FUNC(2))
-#define GPJ12_CAM_B_HREF	(GPJ12 | FUNC(3))
-#define GPJ12_SROM_ADDR_16to222	(GPJ12 | FUNC(4))
-#define GPJ12_MHL_D3		(GPJ12 | FUNC(5))
-#define GPJ13			(PIN(19,3) | PUD)
-#define GPJ13_GPIO		(GPJ13 | FUNC(0))
-#define GPJ13_MSM_ADDR11	(GPJ13 | FUNC(2))
-#define GPJ13_CAM_B_FIELD	(GPJ13 | FUNC(3))
-#define GPJ13_SROM_ADDR_16to223	(GPJ13 | FUNC(4))
-#define GPJ13_MHL_D4		(GPJ13 | FUNC(5))
-#define GPJ14			(PIN(19,4) | PUD)
-#define GPJ14_GPIO		(GPJ14 | FUNC(0))
-#define GPJ14_MSM_ADDR12	(GPJ14 | FUNC(2))
-#define GPJ14_CAM_B_CLKOUT	(GPJ14 | FUNC(3))
-#define GPJ14_SROM_ADDR_16to224	(GPJ14 | FUNC(4))
-#define GPJ14_MHL_D5		(GPJ14 | FUNC(5))
-#define GPJ15			(PIN(19,5) | PUD)
-#define GPJ15_GPIO		(GPJ15 | FUNC(0))
-#define GPJ15_MSM_ADDR13	(GPJ15 | FUNC(2))
-#define GPJ15_KP_COL0		(GPJ15 | FUNC(3))
-#define GPJ15_SROM_ADDR_16to225	(GPJ15 | FUNC(4))
-#define GPJ15_MHL_D6		(GPJ15 | FUNC(5))
-
-/*
- * Group J2: GPIO 0...7
- */
-#define GPJ20		(PIN(20,0) | PUD)
-#define GPJ20_GPIO	(GPJ20 | FUNC(0))
-#define GPJ20_MSM_DATA0	(GPJ20 | FUNC(2))
-#define GPJ20_KP_COL1	(GPJ20 | FUNC(3))
-#define GPJ20_CF_DATA0	(GPJ20 | FUNC(4))
-#define GPJ20_MHL_D7	(GPJ20 | FUNC(5))
-#define GPJ21		(PIN(20,1) | PUD)
-#define GPJ21_GPIO	(GPJ21 | FUNC(0))
-#define GPJ21_MSM_DATA1	(GPJ21 | FUNC(2))
-#define GPJ21_KP_COL2	(GPJ21 | FUNC(3))
-#define GPJ21_CF_DATA1	(GPJ21 | FUNC(4))
-#define GPJ21_MHL_D8	(GPJ21 | FUNC(5))
-#define GPJ22		(PIN(20,2) | PUD)
-#define GPJ22_GPIO	(GPJ22 | FUNC(0))
-#define GPJ22_MSM_DATA2	(GPJ22 | FUNC(2))
-#define GPJ22_KP_COL3	(GPJ22 | FUNC(3))
-#define GPJ22_CF_DATA2	(GPJ22 | FUNC(4))
-#define GPJ22_MHL_D9	(GPJ22 | FUNC(5))
-#define GPJ23		(PIN(20,3) | PUD)
-#define GPJ23_GPIO	(GPJ23 | FUNC(0))
-#define GPJ23_MSM_DATA3	(GPJ23 | FUNC(2))
-#define GPJ23_KP_COL4	(GPJ23 | FUNC(3))
-#define GPJ23_CF_DATA3	(GPJ23 | FUNC(4))
-#define GPJ23_MHL_D10	(GPJ23 | FUNC(5))
-#define GPJ24		(PIN(20,4) | PUD)
-#define GPJ24_GPIO	(GPJ24 | FUNC(0))
-#define GPJ24_MSM_DATA4	(GPJ24 | FUNC(2))
-#define GPJ24_KP_COL5	(GPJ24 | FUNC(3))
-#define GPJ24_CF_DATA4	(GPJ24 | FUNC(4))
-#define GPJ24_MHL_D11	(GPJ24 | FUNC(5))
-#define GPJ25		(PIN(20,5) | PUD)
-#define GPJ25_GPIO	(GPJ25 | FUNC(0))
-#define GPJ25_MSM_DATA5	(GPJ25 | FUNC(2))
-#define GPJ25_KP_COL6	(GPJ25 | FUNC(3))
-#define GPJ25_CF_DATA5	(GPJ25 | FUNC(4))
-#define GPJ25_MHL_D12	(GPJ25 | FUNC(5))
-#define GPJ26		(PIN(20,6) | PUD)
-#define GPJ26_GPIO	(GPJ26 | FUNC(0))
-#define GPJ26_MSM_DATA6	(GPJ26 | FUNC(2))
-#define GPJ26_KP_COL7	(GPJ26 | FUNC(3))
-#define GPJ26_CF_DATA6	(GPJ26 | FUNC(4))
-#define GPJ26_MHL_D13	(GPJ26 | FUNC(5))
-#define GPJ27		(PIN(20,7) | PUD)
-#define GPJ27_GPIO	(GPJ27 | FUNC(0))
-#define GPJ27_MSM_DATA7	(GPJ27 | FUNC(2))
-#define GPJ27_KP_ROW0	(GPJ27 | FUNC(3))
-#define GPJ27_CF_DATA7	(GPJ27 | FUNC(4))
-#define GPJ27_MHL_D14	(GPJ27 | FUNC(5))
-
-/*
- * Group J3: GPIO 0...7
- */
-#define GPJ30			(PIN(21,0) | PUD)
-#define GPJ30_GPIO		(GPJ30 | FUNC(0))
-#define GPJ30_MSM_DATA8		(GPJ30 | FUNC(2))
-#define GPJ30_KP_ROW1		(GPJ30 | FUNC(3))
-#define GPJ30_CF_DATA8		(GPJ30 | FUNC(4))
-#define GPJ30_MHL_D15		(GPJ30 | FUNC(5))
-#define GPJ31			(PIN(21,1) | PUD)
-#define GPJ31_GPIO		(GPJ31 | FUNC(0))
-#define GPJ31_MSM_DATA9		(GPJ31 | FUNC(2))
-#define GPJ31_KP_ROW2		(GPJ31 | FUNC(3))
-#define GPJ31_CF_DATA9		(GPJ31 | FUNC(4))
-#define GPJ31_MHL_D16		(GPJ31 | FUNC(5))
-#define GPJ32			(PIN(21,2) | PUD)
-#define GPJ32_GPIO		(GPJ32 | FUNC(0))
-#define GPJ32_MSM_DATA10	(GPJ32 | FUNC(2))
-#define GPJ32_KP_ROW3		(GPJ32 | FUNC(3))
-#define GPJ32_CF_DATA10		(GPJ32 | FUNC(4))
-#define GPJ32_MHL_D17		(GPJ32 | FUNC(5))
-#define GPJ33			(PIN(21,3) | PUD)
-#define GPJ33_GPIO		(GPJ33 | FUNC(0))
-#define GPJ33_MSM_DATA11	(GPJ33 | FUNC(2))
-#define GPJ33_KP_ROW4		(GPJ33 | FUNC(3))
-#define GPJ33_CF_DATA11		(GPJ33 | FUNC(4))
-#define GPJ33_MHL_D18		(GPJ33 | FUNC(5))
-#define GPJ34			(PIN(21,4) | PUD)
-#define GPJ34_GPIO		(GPJ34 | FUNC(0))
-#define GPJ34_MSM_DATA12	(GPJ34 | FUNC(2))
-#define GPJ34_KP_ROW5		(GPJ34 | FUNC(3))
-#define GPJ34_CF_DATA12		(GPJ34 | FUNC(4))
-#define GPJ34_MHL_D19		(GPJ34 | FUNC(5))
-#define GPJ35			(PIN(21,5) | PUD)
-#define GPJ35_GPIO		(GPJ35 | FUNC(0))
-#define GPJ35_MSM_DATA13	(GPJ35 | FUNC(2))
-#define GPJ35_KP_ROW6		(GPJ35 | FUNC(3))
-#define GPJ35_CF_DATA13		(GPJ35 | FUNC(4))
-#define GPJ35_MHL_D20		(GPJ35 | FUNC(5))
-#define GPJ36			(PIN(21,6) | PUD)
-#define GPJ36_GPIO		(GPJ36 | FUNC(0))
-#define GPJ36_MSM_DATA14	(GPJ36 | FUNC(2))
-#define GPJ36_KP_ROW7		(GPJ36 | FUNC(3))
-#define GPJ36_CF_DATA14		(GPJ36 | FUNC(4))
-#define GPJ36_MHL_D21		(GPJ36 | FUNC(5))
-#define GPJ37			(PIN(21,7) | PUD)
-#define GPJ37_GPIO		(GPJ37 | FUNC(0))
-#define GPJ37_MSM_DATA15	(GPJ37 | FUNC(2))
-#define GPJ37_KP_ROW8		(GPJ37 | FUNC(3))
-#define GPJ37_CF_DATA15		(GPJ37 | FUNC(4))
-#define GPJ37_MHL_D22		(GPJ37 | FUNC(5))
-
-/*
- * Group J4: GPIO 0...4
- */
-#define GPJ40		(PIN(22,0) | PUD)
-#define GPJ40_GPIO	(GPJ40 | FUNC(0))
-#define GPJ40_MSM_NCS	(GPJ40 | FUNC(2))
-#define GPJ40_KP_ROW9	(GPJ40 | FUNC(3))
-#define GPJ40_CF_NCS0	(GPJ40 | FUNC(4))
-#define GPJ40_MHL_D23	(GPJ40 | FUNC(5))
-#define GPJ41		(PIN(22,1) | PUD)
-#define GPJ41_GPIO	(GPJ41 | FUNC(0))
-#define GPJ41_MSM_NWE	(GPJ41 | FUNC(2))
-#define GPJ41_KP_ROW10	(GPJ41 | FUNC(3))
-#define GPJ41_CF_NCS1	(GPJ41 | FUNC(4))
-#define GPJ41_MHL_IDCK	(GPJ41 | FUNC(5))
-#define GPJ42		(PIN(22,2) | PUD)
-#define GPJ42_GPIO	(GPJ42 | FUNC(0))
-#define GPJ42_MSM_NR	(GPJ42 | FUNC(2))
-#define GPJ42_KP_ROW11	(GPJ42 | FUNC(3))
-#define GPJ42_CF_IORN	(GPJ42 | FUNC(4))
-#define GPJ42_MHL_IDCK	(GPJ42 | FUNC(5))
-#define GPJ43		(PIN(22,3) | PUD)
-#define GPJ43_GPIO	(GPJ43 | FUNC(0))
-#define GPJ43_MSM_NIRQ	(GPJ43 | FUNC(2))
-#define GPJ43_KP_ROW12	(GPJ43 | FUNC(3))
-#define GPJ43_CF_IOWN	(GPJ43 | FUNC(4))
-#define GPJ43_MHL_VSYNC	(GPJ43 | FUNC(5))
-#define GPJ44		(PIN(22,4) | PUD)
-#define GPJ44_GPIO	(GPJ44 | FUNC(0))
-#define GPJ44_MSM_ADVN	(GPJ44 | FUNC(2))
-#define GPJ44_KP_ROW13	(GPJ44 | FUNC(3))
-#define GPJ44_SROM_ADDR_16to226	(GPJ44 | FUNC(4))
-#define GPJ44_MHL_DE	(GPJ44 | FUNC(5))
-
-#endif /* __MACH_IOMUX_S5PCXX_H */
diff --git a/arch/arm/mach-samsung/include/mach/iomux.h b/arch/arm/mach-samsung/include/mach/iomux.h
deleted file mode 100644
index 48651d85c3..0000000000
--- a/arch/arm/mach-samsung/include/mach/iomux.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_MACH_IOMUX_H
-#define __ASM_MACH_IOMUX_H
-
-#ifdef CONFIG_ARCH_S3C24xx
-# include <mach/iomux-s3c24x0.h>
-#endif
-#ifdef CONFIG_ARCH_S3C64xx
-# include <mach/iomux-s3c64xx.h>
-#endif
-#ifdef CONFIG_ARCH_S5PCxx
-# include <mach/iomux-s5pcxx.h>
-#endif
-
-void s3c_gpio_mode(unsigned);
-
-#endif /* __ASM_MACH_IOMUX_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-busctl.h b/arch/arm/mach-samsung/include/mach/s3c-busctl.h
deleted file mode 100644
index 4bcf0a7013..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c-busctl.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2011 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_S3C_BUSCTL_H
-# define __MACH_S3C_BUSCTL_H
-
-#define S3C_BWSCON (S3C_MEMCTL_BASE)
-#define S3C_BANKCON0 (S3C_MEMCTL_BASE + 0x04)
-#define S3C_BANKCON1 (S3C_MEMCTL_BASE + 0x08)
-#define S3C_BANKCON2 (S3C_MEMCTL_BASE + 0x0c)
-#define S3C_BANKCON3 (S3C_MEMCTL_BASE + 0x10)
-#define S3C_BANKCON4 (S3C_MEMCTL_BASE + 0x14)
-#define S3C_BANKCON5 (S3C_MEMCTL_BASE + 0x18)
-#define S3C_BANKCON6 (S3C_MEMCTL_BASE + 0x1c)
-#define S3C_BANKCON7 (S3C_MEMCTL_BASE + 0x20)
-#define S3C_REFRESH (S3C_MEMCTL_BASE + 0x24)
-#define S3C_BANKSIZE (S3C_MEMCTL_BASE + 0x28)
-#define S3C_MRSRB6 (S3C_MEMCTL_BASE + 0x2c)
-#define S3C_MRSRB7 (S3C_MEMCTL_BASE + 0x30)
-
-#endif /* __MACH_S3C_BUSCTL_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-clocks.h b/arch/arm/mach-samsung/include/mach/s3c-clocks.h
deleted file mode 100644
index ef7900285c..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c-clocks.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-#ifndef __MACH_S3C_CLOCKS_H
-#define __MACH_S3C_CLOCKS_H
-
-#ifdef CONFIG_ARCH_S3C24xx
-# include <mach/s3c24xx-clocks.h>
-#endif
-#ifdef CONFIG_ARCH_S3C64xx
-# include <mach/s3c64xx-clocks.h>
-#endif
-#ifdef CONFIG_ARCH_S5PCxx
-# include <mach/s5pcxx-clocks.h>
-#endif
-
-#endif /* __MACH_S3C_CLOCKS_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h b/arch/arm/mach-samsung/include/mach/s3c-generic.h
deleted file mode 100644
index 27f264ce25..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c-generic.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * (C) Copyright 2009
- * Juergen Beisert, Pengutronix
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller at elsoft.ch
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-
-uint32_t s3c_get_mpllclk(void);
-uint32_t s3c_get_upllclk(void);
-uint32_t s3c_get_fclk(void);
-uint32_t s3c_get_hclk(void);
-uint32_t s3c_get_pclk(void);
-uint32_t s3c_get_uclk(void);
-
-unsigned s3c_get_uart_clk(unsigned src);
-
-#ifdef CONFIG_ARCH_S3C24xx
-uint32_t s3c24xx_get_memory_size(void);
-void s3c24xx_disable_second_sdram_bank(void);
-#endif
-
-#ifdef CONFIG_ARCH_S5PCxx
-void s5p_init_pll(void);
-void s5p_init_dram_bank_lpddr(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16);
-void s5p_init_dram_bank_lpddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16);
-void s5p_init_dram_bank_ddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16);
-uint32_t s5p_get_memory_size(void);
-#endif
-
-#ifdef CONFIG_ARCH_S3C64xx
-unsigned s3c_set_epllclk(unsigned, unsigned, unsigned, unsigned);
-uint32_t s3c_get_epllclk(void);
-unsigned s3c_get_hsmmc_clk(int);
-void s3c_set_hsmmc_clk(int, int, unsigned);
-unsigned s3c6410_get_memory_size(void);
-struct s3c6410_chipselect {
-	unsigned adr_setup_t; /* in [ns] */
-	unsigned access_setup_t; /* in [ns] */
-	unsigned access_t; /* in [ns] */
-	unsigned cs_hold_t; /* in [ns] */
-	unsigned adr_hold_t; /* in [ns] */
-	unsigned char width; /* 8 or 16 */
-};
-int s3c6410_setup_chipselect(int, const struct s3c6410_chipselect*);
-#endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
deleted file mode 100644
index 67fb18e5b2..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-#ifdef CONFIG_ARCH_S3C24xx
-# include <mach/s3c24xx-iomap.h>
-#endif
-#ifdef CONFIG_ARCH_S3C64xx
-# include <mach/s3c64xx-iomap.h>
-#endif
-#ifdef CONFIG_ARCH_S5PCxx
-# include <mach/s5pcxx-iomap.h>
-#endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c-mci.h b/arch/arm/mach-samsung/include/mach/s3c-mci.h
deleted file mode 100644
index d3ffb5e637..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c-mci.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * (C) Copyright 2010 Juergen Beisert, Pengutronix
- *
- * This code is partially based on u-boot code:
- *
- * Copyright 2008, Freescale Semiconductor, Inc
- * Andy Fleming
- *
- * Based (loosely) on the Linux code
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_MMC_H_
-#define __MACH_MMC_H_
-
-struct s3c_mci_platform_data {
-	unsigned caps;	/**< supported operating modes (MMC_MODE_*) */
-	unsigned voltages; /**< supported voltage range (MMC_VDD_*) */
-	unsigned f_min;	/**< min operating frequency in Hz (0 -> no limit) */
-	unsigned f_max;	/**< max operating frequency in Hz (0 -> no limit) */
-	/* TODO */
-	/* function to modify the voltage */
-	/* function to switch the voltage */
-	/* function to detect the presence of a SD card in the socket */
-	unsigned gpio_detect;
-	unsigned detect_invert;
-};
-
-#endif /* __MACH_MMC_H_ */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-clocks.h b/arch/arm/mach-samsung/include/mach/s3c24xx-clocks.h
deleted file mode 100644
index 839dfe3c99..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-clocks.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2011 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-# define S3C_LOCKTIME (S3C_CLOCK_POWER_BASE)
-# define S3C_MPLLCON (S3C_CLOCK_POWER_BASE + 0x4)
-# define S3C_UPLLCON (S3C_CLOCK_POWER_BASE + 0x8)
-# define S3C_CLKCON (S3C_CLOCK_POWER_BASE + 0xc)
-# define S3C_CLKSLOW (S3C_CLOCK_POWER_BASE + 0x10)
-# define S3C_CLKDIVN (S3C_CLOCK_POWER_BASE + 0x14)
-
-# define S3C_MPLLCON_GET_MDIV(x) ((((x) >> 12) & 0xff) + 8)
-# define S3C_MPLLCON_GET_PDIV(x) ((((x) >> 4) & 0x3f) + 2)
-# define S3C_MPLLCON_GET_SDIV(x) ((x) & 0x3)
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h b/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
deleted file mode 100644
index 2fa48e7c3c..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2010 Juergen Beisert
- * Copyright (C) 2011 Alexey Galakhov
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-#ifndef __MACH_FB_H_
-# define __MACH_FB_H_
-
-#include <fb.h>
-
-/** Proprietary flags corresponding to  S3C24x0 LCDCON5 register */
-
-/** ! INVVDEN - DE active high */
-#define FB_SYNC_DE_HIGH_ACT	(1 << 23)
-/** INVVCLK - invert CLK signal */
-#define FB_SYNC_CLK_INVERT	(1 << 24)
-/** INVVD - invert data */
-#define FB_SYNC_DATA_INVERT	(1 << 25)
-/** INVPWREN - use PWREN signal */
-#define FB_SYNC_INVERT_PWREN	(1 << 26)
-/** INVLEND - use LEND signal */
-#define FB_SYNC_INVERT_LEND	(1 << 27)
-/** PWREN - use PWREN signal */
-#define FB_SYNC_USE_PWREN	(1 << 28)
-/** ENLEND - use LEND signal */
-#define FB_SYNC_USE_LEND	(1 << 29)
-/** BSWP - swap bytes */
-#define FB_SYNC_SWAP_BYTES	(1 << 30)
-/** HWSWP - swap half words */
-#define FB_SYNC_SWAP_HW		(1 << 31)
-
-struct s3c_fb_platform_data {
-	struct fb_videomode *mode_list;
-	unsigned mode_cnt;
-
-	unsigned bits_per_pixel;
-	int passive_display;	/**< enable support for STN or CSTN displays */
-
-	/** hook to enable backlight and stuff */
-	void (*enable)(int enable);
-};
-
-#endif /* __MACH_FB_H_ */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h b/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
deleted file mode 100644
index ffb57fbd1f..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2011 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_GPIO_S3C24X0_H
-# define __MACH_GPIO_S3C24X0_H
-
-#define S3C_GPACON (S3C_GPIO_BASE)
-#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
-
-#define S3C_GPBCON (S3C_GPIO_BASE + 0x10)
-#define S3C_GPBDAT (S3C_GPIO_BASE + 0x14)
-#define S3C_GPBUP (S3C_GPIO_BASE + 0x18)
-
-#define S3C_GPCCON (S3C_GPIO_BASE + 0x20)
-#define S3C_GPCDAT (S3C_GPIO_BASE + 0x24)
-#define S3C_GPCUP (S3C_GPIO_BASE + 0x28)
-
-#define S3C_GPDCON (S3C_GPIO_BASE + 0x30)
-#define S3C_GPDDAT (S3C_GPIO_BASE + 0x34)
-#define S3C_GPDUP (S3C_GPIO_BASE + 0x38)
-
-#define S3C_GPECON (S3C_GPIO_BASE + 0x40)
-#define S3C_GPEDAT (S3C_GPIO_BASE + 0x44)
-#define S3C_GPEUP (S3C_GPIO_BASE + 0x48)
-
-#define S3C_GPFCON (S3C_GPIO_BASE + 0x50)
-#define S3C_GPFDAT (S3C_GPIO_BASE + 0x54)
-#define S3C_GPFUP (S3C_GPIO_BASE + 0x58)
-
-#define S3C_GPGCON (S3C_GPIO_BASE + 0x60)
-#define S3C_GPGDAT (S3C_GPIO_BASE + 0x64)
-#define S3C_GPGUP (S3C_GPIO_BASE + 0x68)
-
-#define S3C_GPHCON (S3C_GPIO_BASE + 0x70)
-#define S3C_GPHDAT (S3C_GPIO_BASE + 0x74)
-#define S3C_GPHUP (S3C_GPIO_BASE + 0x78)
-
-#ifdef CONFIG_CPU_S3C2440
-# define S3C_GPJCON (S3C_GPIO_BASE + 0xd0)
-# define S3C_GPJDAT (S3C_GPIO_BASE + 0xd4)
-# define S3C_GPJUP (S3C_GPIO_BASE + 0xd8)
-#endif
-
-#define S3C_MISCCR  (S3C_GPIO_BASE + 0x80)
-#define S3C_DCLKCON (S3C_GPIO_BASE + 0x84)
-#define S3C_EXTINT0 (S3C_GPIO_BASE + 0x88)
-#define S3C_EXTINT1 (S3C_GPIO_BASE + 0x8c)
-#define S3C_EXTINT2 (S3C_GPIO_BASE + 0x90)
-#define S3C_EINTFLT0 (S3C_GPIO_BASE + 0x94)
-#define S3C_EINTFLT1 (S3C_GPIO_BASE + 0x98)
-#define S3C_EINTFLT2 (S3C_GPIO_BASE + 0x9c)
-#define S3C_EINTFLT3 (S3C_GPIO_BASE + 0xa0)
-#define S3C_EINTMASK (S3C_GPIO_BASE + 0xa4)
-#define S3C_EINTPEND (S3C_GPIO_BASE + 0xa8)
-#define S3C_GSTATUS0 (S3C_GPIO_BASE + 0xac)
-#define S3C_GSTATUS1 (S3C_GPIO_BASE + 0xb0)
-#define S3C_GSTATUS2 (S3C_GPIO_BASE + 0xb4)
-#define S3C_GSTATUS3 (S3C_GPIO_BASE + 0xb8)
-#define S3C_GSTATUS4 (S3C_GPIO_BASE + 0xbc)
-
-#ifdef CONFIG_CPU_S3C2440
-# define S3C_DSC0 (S3C_GPIO_BASE + 0xc4)
-# define S3C_DSC1 (S3C_GPIO_BASE + 0xc8)
-#endif
-
-#endif /* __MACH_GPIO_S3C24X0_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-iomap.h b/arch/arm/mach-samsung/include/mach/s3c24xx-iomap.h
deleted file mode 100644
index ada23042fb..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-iomap.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2009 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-/* S3C2410 device base addresses */
-#define S3C_MEMCTL_BASE			0x48000000
-#define S3C2410_USB_HOST_BASE		0x49000000
-#define S3C2410_INTERRUPT_BASE		0x4A000000
-#define S3C2410_DMA_BASE		0x4B000000
-#define S3C_CLOCK_POWER_BASE		0x4C000000
-#define S3C2410_LCD_BASE		0x4D000000
-#define S3C24X0_NAND_BASE		0x4E000000
-#define S3C_UART_BASE			0x50000000
-#define S3C_TIMER_BASE			0x51000000
-#define S3C2410_USB_DEVICE_BASE		0x52000140
-#define S3C_WATCHDOG_BASE		0x53000000
-#define S3C2410_I2C_BASE		0x54000000
-#define S3C2410_I2S_BASE		0x55000000
-#define S3C_GPIO_BASE			0x56000000
-#define S3C2410_RTC_BASE		0x57000000
-#define S3C2410_ADC_BASE		0x58000000
-#define S3C2410_SPI_BASE		0x59000000
-#define S3C2410_SDI_BASE		0x5A000000
-
-/* external IO space */
-#define S3C_CS0_BASE 0x00000000
-#define S3C_CS1_BASE 0x08000000
-#define S3C_CS2_BASE 0x10000000
-#define S3C_CS3_BASE 0x18000000
-#define S3C_CS4_BASE 0x20000000
-#define S3C_CS5_BASE 0x28000000
-#define S3C_CS6_BASE 0x30000000
-
-#define S3C_SDRAM_BASE S3C_CS6_BASE
-#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
-
-/*
- * if we are booting from NAND, its internal SRAM occures at
- * a different address than without this feature
- */
-#ifdef CONFIG_S3C_NAND_BOOT
-# define NFC_RAM_AREA 0x00000000
-#else
-# define NFC_RAM_AREA 0x40000000
-#endif
-#define NFC_RAM_SIZE 4096
-
-#define S3C_UART1_BASE (S3C_UART_BASE)
-#define S3C_UART1_SIZE 0x4000
-#define S3C_UART2_BASE (S3C_UART_BASE + 0x4000)
-#define S3C_UART2_SIZE 0x4000
-#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
-#define S3C_UART3_SIZE 0x4000
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
deleted file mode 100644
index 52642ee81f..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (C) 2009 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-#ifndef MACH_S3C24XX_NAND_H
-# define MACH_S3C24XX_NAND_H
-
-#ifdef CONFIG_S3C_NAND_BOOT
-extern void s3c24x0_nand_load_image(void*, int, int);
-#endif
-
-/**
- * Locate the timing bits for the NFCONF register
- * @param setup is the TACLS clock count
- * @param access is the TWRPH0 clock count
- * @param hold is the TWRPH1 clock count
- *
- * @note A clock count of 0 means always 1 HCLK clock.
- * @note Clock count settings depend on the NAND flash requirements and the current HCLK speed
- */
-#ifdef CONFIG_CPU_S3C2410
-# define CALC_NFCONF_TIMING(setup, access, hold) \
-	((setup << 8) + (access << 4) + (hold << 0))
-#endif
-#ifdef CONFIG_CPU_S3C2440
-# define CALC_NFCONF_TIMING(setup, access, hold) \
-	((setup << 12) + (access << 8) + (hold << 4))
-#endif
-
-/**
- * Define platform specific data for the NAND controller and its device
- */
-struct s3c24x0_nand_platform_data {
-	uint32_t nand_timing;	/**< value for the NFCONF register (timing bits only) */
-	char flash_bbt;	/**< force a flash based BBT */
-};
-
-/**
- * @file
- * @brief Basic declaration to use the s3c24x0 NAND driver
- */
-
-void nand_boot(void);
-
-#endif /* MACH_S3C24XX_NAND_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h b/arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h
deleted file mode 100644
index 8aa60bcb04..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define S3C_EPLL_LOCK  (S3C_CLOCK_POWER_BASE + 0x08)
-# define S3C_EPLL_LOCK_PLL_LOCKTIME(x) ((x) & 0xffff)
-#define S3C_APLLCON (S3C_CLOCK_POWER_BASE + 0x0c)
-# define S3C_APLLCON_ENABLE (1 << 31)
-# define S3C_APLLCON_GET_MDIV(x) (((x) >> 16) & 0x3ff)
-# define S3C_APLLCON_GET_PDIV(x) (((x) >> 8) & 0x3f)
-# define S3C_APLLCON_GET_SDIV(x) ((x) & 0x7)
-#define S3C_MPLLCON (S3C_CLOCK_POWER_BASE + 0x10)
-# define S3C_MPLLCON_ENABLE (1 << 31)
-# define S3C_MPLLCON_GET_MDIV(x) (((x) >> 16) & 0x3ff)
-# define S3C_MPLLCON_GET_PDIV(x) (((x) >> 8) & 0x3f)
-# define S3C_MPLLCON_GET_SDIV(x) ((x) & 0x7)
-#define S3C_EPLLCON0 (S3C_CLOCK_POWER_BASE + 0x14)
-# define S3C_EPLLCON0_ENABLE (1 << 31)
-# define S3C_EPLLCON0_GET_MDIV(x) (((x) >> 16) & 0xff)
-# define S3C_EPLLCON0_SET_MDIV(x) (((x) & 0xff) << 16)
-# define S3C_EPLLCON0_GET_PDIV(x) (((x) >> 8) & 0x3f)
-# define S3C_EPLLCON0_SET_PDIV(x) (((x) & 0x3f) << 8)
-# define S3C_EPLLCON0_GET_SDIV(x) ((x) & 0x7)
-# define S3C_EPLLCON0_SET_SDIV(x) ((x) & 0x7)
-#define S3C_EPLLCON1 (S3C_CLOCK_POWER_BASE + 0x18)
-# define S3C_EPLLCON1_GET_KDIV(x) ((x) & 0xffff)
-# define S3C_EPLLCON1_SET_KDIV(x) ((x) & 0xffff)
-#define S3C_CLKCON (S3C_CLOCK_POWER_BASE + 0xc)
-#define S3C_CLKSLOW (S3C_CLOCK_POWER_BASE + 0x10)
-#define S3C_CLKDIVN (S3C_CLOCK_POWER_BASE + 0x14)
-#define S3C_CLK_SRC (S3C_CLOCK_POWER_BASE + 0x01c)
-# define S3C_CLK_SRC_GET_MMC_SEL(x, v) (((v) >> (18 + (x * 2))) & 0x3)
-# define S3C_CLK_SRC_SET_MMC_SEL(x, v) (((v) & 0x3) << (18 + (x * 2)))
-# define S3C_CLK_SRC_UARTMPLL (1 << 13)
-# define S3C_CLK_SRC_FOUTEPLL (1 << 2)
-# define S3C_CLK_SRC_FOUTMPLL (1 << 1)
-# define S3C_CLK_SRC_FOUTAPLL (1 << 0)
-#define S3C_CLK_DIV0 (S3C_CLOCK_POWER_BASE + 0x020)
-# define S3C_CLK_DIV0_GET_ADIV(x) ((x) & 0xf)
-# define S3C_CLK_DIV0_GET_HCLK2(x) (((x) >> 9) & 0x7)
-# define S3C_CLK_DIV0_GET_HCLK(x) (((x) >> 8) & 0x1)
-# define S3C_CLK_DIV0_GET_PCLK(x) (((x) >> 12) & 0xf)
-# define S3C_CLK_DIV0_SET_MPLL_DIV(x) (((x) & 0x1) << 4)
-# define S3C_CLK_DIV0_GET_MPLL_DIV(x) (((x) >> 4) & 0x1)
-# define S3C_CLK_DIV0_GET_MMC(x, v) (((v) >> (4 * x)) & 0xf)
-# define S3C_CLK_DIV0_SET_MMC(x, v) (((v) & 0xf) << (4 * x))
-#define S3C_CLK_DIV2 (S3C_CLOCK_POWER_BASE + 0x028)
-# define S3C_CLK_DIV2_UART_MASK (0xf << 16)
-# define S3C_CLK_DIV2_SET_UART(x) ((x) << 16)
-# define S3C_CLK_DIV2_GET_UART(x) (((x) >> 16) & 0xf)
-#define S3C_SCLK_GATE (S3C_CLOCK_POWER_BASE + 0x038)
-# define S3C_SCLK_GATE_UART (1 << 5)
-# define S3C_SCLK_GATE_MMC(x) (1 << (24 + x))
-#define S3C_MISC_CON (S3C_CLOCK_POWER_BASE + 0x838)
-# define S3C_MISC_CON_SYN667 (1 << 19)
-#define S3C_OTHERS (S3C_CLOCK_POWER_BASE + 0x900)
-# define S3C_OTHERS_CLK_SELECT (1 << 6)
diff --git a/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h b/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
deleted file mode 100644
index 9cc3a1bcba..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* S3C64xx device base addresses */
-#define S3C_SROM_SFR		0x70000000
-#define S3C_NAND_BASE		0x70200000
-#define S3C_SDI0_BASE		0x7c200000
-#define S3C_SDI0_SIZE		0x100
-#define S3C_SDI1_BASE		0x7c300000
-#define S3C_SDI1_SIZE		0x100
-#define S3C_SDI2_BASE		0x7c400000
-#define S3C_SDI2_SIZE		0x100
-#define S3C_DRAMC		0x7e001000
-#define S3C_WATCHDOG_BASE	0x7e004000
-#define S3C_CLOCK_POWER_BASE	0x7e00f000
-#define S3C_UART_BASE		0x7f005000
-#define S3C_TIMER_BASE		0x7f006000
-#define S3C_GPIO_BASE		0x7f008000
-
-#define S3C_UART1_BASE (S3C_UART_BASE)
-#define S3C_UART1_SIZE 0x400
-#define S3C_UART2_BASE (S3C_UART_BASE + 0x400)
-#define S3C_UART2_SIZE 0x400
-#define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
-#define S3C_UART3_SIZE 0x400
-#define S3C_UART4_BASE (S3C_UART_BASE + 0xc00)
-#define S3C_UART4_SIZE 0x400
-
-#define S3C_SDRAM_BASE 0x50000000
-#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
-
-#define S3C_SROM_BW (S3C_SROM_SFR)
-#define S3C_SROM_BC0 (S3C_SROM_SFR + 4)
-
-#define S3C_CS0_BASE 0x10000000
-#define S3C_CS1_BASE 0x18000000
-#define S3C_CS2_BASE 0x20000000
-#define S3C_CS3_BASE 0x28000000
-#define S3C_CS4_BASE 0x30000000
-#define S3C_CS5_BASE 0x38000000
diff --git a/arch/arm/mach-samsung/include/mach/s5pcxx-clocks.h b/arch/arm/mach-samsung/include/mach/s5pcxx-clocks.h
deleted file mode 100644
index f9d49c5156..0000000000
--- a/arch/arm/mach-samsung/include/mach/s5pcxx-clocks.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-# define S5P_APLL 0x00
-# define S5P_MPLL 0x08
-# define S5P_EPLL 0x10
-# define S5P_VPLL 0x20
-# define S5P_xPLL_LOCK (S5P_CLOCK_POWER_BASE)
-# define S5P_xPLL_CON  (S5P_CLOCK_POWER_BASE + 0x100)
-# define S5P_xPLL_CON0 (S5P_xPLL_CON)
-# define S5P_xPLL_CON1 (S5P_xPLL_CON + 0x4)
-
-# define S5P_xPLLCON_GET_MDIV(x)  (((x) >> 16) & 0x3ff)
-# define S5P_xPLLCON_GET_PDIV(x)  (((x) >> 8) & 0x3f)
-# define S5P_xPLLCON_GET_SDIV(x)  ((x) & 0x3)
-
-# define S5P_CLK_SRC0 (S5P_CLOCK_POWER_BASE + 0x200)
-# define S5P_CLK_SRC1 (S5P_CLOCK_POWER_BASE + 0x204)
-# define S5P_CLK_SRC2 (S5P_CLOCK_POWER_BASE + 0x208)
-# define S5P_CLK_SRC3 (S5P_CLOCK_POWER_BASE + 0x20C)
-# define S5P_CLK_SRC4 (S5P_CLOCK_POWER_BASE + 0x210)
-# define S5P_CLK_SRC5 (S5P_CLOCK_POWER_BASE + 0x214)
-# define S5P_CLK_SRC6 (S5P_CLOCK_BASE + 0x218)
-
-# define S5P_CLK_DIV0 (S5P_CLOCK_POWER_BASE + 0x300)
-# define S5P_CLK_DIV1 (S5P_CLOCK_POWER_BASE + 0x304)
-# define S5P_CLK_DIV2 (S5P_CLOCK_POWER_BASE + 0x308)
-# define S5P_CLK_DIV3 (S5P_CLOCK_POWER_BASE + 0x30C)
-# define S5P_CLK_DIV4 (S5P_CLOCK_POWER_BASE + 0x310)
-# define S5P_CLK_DIV5 (S5P_CLOCK_POWER_BASE + 0x314)
-# define S5P_CLK_DIV6 (S5P_CLOCK_POWER_BASE + 0x318)
-# define S5P_CLK_DIV7 (S5P_CLOCK_POWER_BASE + 0x31C)
-
-# define S5P_CLK_GATE_SCLK  (S5P_CLOCK_POWER_BASE + 0x444)
-# define S5P_CLK_GATE_IP0   (S5P_CLOCK_POWER_BASE + 0x460)
-# define S5P_CLK_GATE_IP1   (S5P_CLOCK_POWER_BASE + 0x464)
-# define S5P_CLK_GATE_IP2   (S5P_CLOCK_POWER_BASE + 0x468)
-# define S5P_CLK_GATE_IP3   (S5P_CLOCK_POWER_BASE + 0x46C)
-# define S5P_CLK_GATE_IP4   (S5P_CLOCK_POWER_BASE + 0x470)
-# define S5P_CLK_GATE_BLOCK (S5P_CLOCK_POWER_BASE + 0x480)
-# define S5P_CLK_GATE_IP5   (S5P_CLOCK_POWER_BASE + 0x484)
-
-# define S5P_OTHERS (S5P_CLOCK_POWER_BASE + 0xE000)
-# define S5P_USB_PHY_CONTROL (S5P_CLOCK_POWER_BASE + 0xE80C)
diff --git a/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h b/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
deleted file mode 100644
index c0f763371b..0000000000
--- a/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-/* S5PV210 device base addresses */
-
-#define S5P_CLOCK_POWER_BASE	0xE0100000
-#define S3C_GPIO_BASE		0xE0200000
-#define S3C_TIMER_BASE		0xE2500000
-#define S3C_WATCHDOG_BASE	0xE2700000
-#define S3C_UART_BASE		0xE2900000
-#define S3C_USB_HOST_BASE	0xEC200000
-#define S3C_NAND_BASE		0xB0E00000
-
-/* external IO space */
-#define S3C_CS0_BASE 0x80000000
-#define S3C_CS1_BASE 0x88000000
-#define S3C_CS2_BASE 0x90000000
-#define S3C_CS3_BASE 0x98000000
-#define S3C_CS4_BASE 0xA0000000
-#define S3C_CS5_BASE 0xA8000000
-
-#define S3C_SDRAM_BASE 0x20000000
-#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x60000000)
-
-#define S3C_UART1_BASE (S3C_UART_BASE)
-#define S3C_UART1_SIZE 0x400
-#define S3C_UART2_BASE (S3C_UART_BASE + 0x400)
-#define S3C_UART2_SIZE 0x400
-#define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
-#define S3C_UART3_SIZE 0x400
-
-#define S5P_DMC0_BASE 0xF0000000
-#define S5P_DMC1_BASE 0xF1400000
diff --git a/arch/arm/mach-samsung/lowlevel-s3c24x0.S b/arch/arm/mach-samsung/lowlevel-s3c24x0.S
deleted file mode 100644
index d43cdff528..0000000000
--- a/arch/arm/mach-samsung/lowlevel-s3c24x0.S
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * (C) Copyright 2009
- * Juergen Beisert <kernel at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <config.h>
-#include <mach/s3c-iomap.h>
-
-	.section ".text_bare_init.s3c24x0_disable_wd","ax"
-
-/*
- * Disable the watchdog, else it continues to bark
- */
-.globl s3c24x0_disable_wd
-s3c24x0_disable_wd:
-
-	ldr r0, =S3C_WATCHDOG_BASE
-	mov r1, #0x0
-	str r1, [r0]
-	mov pc, lr
-
-/*
- * S3C2410 PLL configuration
- * -------------------------
- *
- * Basic frequency calculation
- *
- *            m * REFclk         s = SDIV
- * PLLclk = ------------         p = PDIV + 2
- *             p * 2^s           m = MDIV + 8
- *
- * After reset the PLL of the s3c2410 processor uses:
- *
- *         MPLL   UPLL
- *  MDIV   0x5c   0x28
- *  PDIV   0x08   0x08
- *  SDIV   0x0    0x0
- *
- *            100 * 12MHz     1200MHz
- * MPLLclk = ------------- = -------- = 120MHz
- *             10 * 2^0         10
- *
- *            48 * 12MHz      576MHz
- * UPLLclk = ------------- = -------- = 57,6MHz
- *             10 * 2^0        10
- *
- * Note: Do not use "r10" here in this code
- */
-
-#ifdef CONFIG_S3C_PLL_INIT
-
-	.section ".text_bare_init.s3c24x0_pll_init","ax"
-
-.globl s3c24x0_pll_init
-s3c24x0_pll_init:
-
-	mov r0, #S3C_CLOCK_POWER_BASE
-
-	/* configure internal clock ratio */
-	mov r1, #BOARD_SPECIFIC_CLKDIVN
-	str r1, [r0, #20]
-
-	/* enable all devices on this chip */
-	mov r1, #0xFFFFFFF0
-	str r1, [r0, #12]
-
-	/* ??????? */
-#ifdef CONFIG_CPU_S3C2440
-	mov r1, #0xFFFFFFFF
-#endif
-#ifdef CONFIG_CPU_S3C2410
-	mov r1, #0x00FFFFFF
-#endif
-	str r1, [r0, #0]
-
-#ifdef CONFIG_CPU_S3C2440
-	/*
-	 * Most of the time HDIVN is not 0, so we must use the
-	 * asynchronous bus mode (refer datasheet "Clock and Power Management")
-	 */
-	mrc p15, 0, r1, c1, c0, 0
-	orr r1, r1, #0xc0000000
-	mcr p15, 0, r1, c1, c0, 0
-#endif
-
-	/* configure UPLL */
-	ldr r1, =BOARD_SPECIFIC_UPLL
-	str r1, [r0, #8]
-
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	/* configure MPLL */
-	ldr r1, =BOARD_SPECIFIC_MPLL
-	str r1, [r0, #4]
-
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	mov pc, lr
-
-#endif
-
-/**
- at page dev_s3c24xx_pll_handling PLL clock handling
-
-To control the speed of your machine the PLLs must be reconfigured after reset.
-
-For example the S3C2410 CPU wakes up after reset at 120MHz main PLL speed,
-shared with all other system on chip components. Most of the time this
-configuration is to slow for the CPU and to fast for the other components.
-
-PLL reprogramming can be done in the machine specific manner very early when
-the CONFIG_S3C_PLL_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT symbols are
-defined. The board must provide a board_init_lowlevel() assembler function in
-this case and calling the s3c24x0_pll_init() assembler function.
-
-If the s3c24x0_pll_init() is called a few further symbols must be defined to
-setup the correct values for the machine.
-
-Define in the machine specific config.h the following symbols:
-
-- S3C24XX_CLOCK_REFERENCE with the frequency in Hz of your reference crystal.
-- BOARD_SPECIFIC_CLKDIVN with the value for the main clock ratio register (CLKDIVN)
-- BOARD_SPECIFIC_MPLL with the value for the main PLL setup register
-- BOARD_SPECIFIC_UPLL with the value for the USB PLL setup register
-
- at note Valid values for the PLL settings can be found in the CPU manual.
-
- at par Background: PLL frequency calculation for the S3C2410 CPU (both PLLs) and S3C2440 (UPLL only)
-
- at f[
-	f_{PLL} = \frac{m * f_{Ref}}{p * 2^s}
- at f]
-
-With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
-
- at par Background: PLL frequency calculation for the S3C2440 CPU (MPLL only)
-
- at f[
-	f_{PLL} = \frac{2 * m * f_{Ref}}{p * 2^s}
- at f]
-
-With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
-
- at note This routine can be used for the S3C2410 and the S3C2440 CPU.
-
-*/
-
-/* ----------------------------------------------------------------------- */
-
-#ifdef CONFIG_S3C_SDRAM_INIT
-
-	.section ".text_bare_init.s3c24x0_sdram_init","ax"
-
-	.globl s3c24x0_sdram_init
-s3c24x0_sdram_init:
-
-	adr r0, SDRAMDATA	/* get the current relative address of the table */
-	mov r1, #S3C_MEMCTL_BASE
-	mov r2, #6		/* we *know* it contains 6 entries */
-
-	ldr r3, [r0], #4	/* write BSWCON first */
-	str r3, [r1], #0x1c	/* post add register offset for bank6 */
-/*
- * Initializing the SDRAM controller is very simple:
- * Just write some useful values into the SDRAM controller.
- */
-0:	ldr r3, [r0], #4
-	str r3, [r1], #4
-	subs r2, r2, #1
-	bne 0b
-
-	mov pc, lr
-
-SDRAMDATA:
-	.word BOARD_SPECIFIC_BWSCON
-	.word BOARD_SPECIFIC_BANKCON6
-	.word BOARD_SPECIFIC_BANKCON7
-	.word BOARD_SPECIFIC_REFRESH
-	.word BOARD_SPECIFIC_BANKSIZE
-	.word BOARD_SPECIFIC_MRSRB6
-	.word BOARD_SPECIFIC_MRSRB7
-
-#endif
-
-/**
- at page dev_s3c24xx_sdram_handling SDRAM controller initialisation
-
-The SDRAM controller is very simple and its initialisation requires only a
-few steps. barebox provides a generic routine to do this step.
-
-Enable CONFIG_S3C_SDRAM_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be able
-to call the generic s3c24x0_sdram_init() assembler function from within the
-machine specific board_init_lowlevel() assembler function.
-
-To use the s3c24x0_sdram_init() assembler function a few symbols must be
-defined to setup correct values for the machine.
-
-Define in the machine specific config.h the following list of symbols:
-
-- BOARD_SPECIFIC_BWSCON with the values for SDRAM banks 6 and 7
-- BOARD_SPECIFIC_BANKCON6 with the value for the BANKCON6 register
-- BOARD_SPECIFIC_BANKCON7 with the value for the BANKCON7 register
-- BOARD_SPECIFIC_REFRESH with the value for the REFRESH register
-- BOARD_SPECIFIC_BANKSIZE with the value for the BANKSIZE register
-- BOARD_SPECIFIC_MRSRB6 with the value for the MRSRB6 register
-- BOARD_SPECIFIC_MRSRB7 with the value for the MRSRB7 register
-*/
-
-/* ----------------------------------------------------------------------- */
-
-#ifdef CONFIG_S3C_NAND_BOOT
-
-	.section ".text_bare_init.s3c24x0_nand_boot","ax"
-
-	.globl s3c24x0_nand_boot
-s3c24x0_nand_boot:
-/*
- * In the case of NOR boot we are running from the same address space.
- * Detect this case to handle it correctly.
- */
-	mov r1, #S3C_MEMCTL_BASE
-	ldr r3, [r1]
-	and r3, r3, #0x6
-	cmp r3, #0x0	/* check for NAND case */
-	beq 2f
-	mov pc, lr	/* NOR case: nothing to do here */
-
-2:	ldr sp, =_text	/* Setup a temporary stack in SDRAM */
-/*
- * We still run at a location we are not linked to. But lets still running
- * from the internal SRAM, this may speed up the boot
- */
-	push {lr}
-	bl nand_boot
-	pop {lr}
-/*
- * Adjust the return address to the correct address in SDRAM
- */
-	ldr r1, =_text
-	add lr, lr, r1
-
-	mov pc, lr
-
-#endif
-
-/**
- at page dev_s3c24xx_nandboot_handling Booting from NAND
-
-To be able to boot from NAND memory only, enable the S3C24x0 NAND driver. Also
-enable CONFIG_S3C_NAND_BOOT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be
-able to call the s3c24x0_nand_boot() assembler routine from within the
-machine specific board_init_lowlevel() assembler function.
-
- at note This routine assumes an already working SDRAM controller and
-an initialized stack pointer.
-
- at note Basicly this routine runs from inside the internal SRAM. After load of
-the whole barebox image from the NAND flash memory into the SDRAM it adjusts
-the link register to the final SDRAM adress and returns.
-
- at note In the NAND boot mode, ECC is not checked. So, the first x KBytes used
-by barebox should have no bit error.
-
-Due to the fact the code to load the whole barebox from NAND must fit into
-the first 4kiB of the barebox image, the shrinked NAND driver is very
-minimalistic. Setup the NAND access timing is done in a safe manner, what
-means: Slowest possible values are used. If you want to increase the speed you
-should define the BOARD_DEFAULT_NAND_TIMING to a valid setting into the
-NFCONF register and add it to your board specific config.h. Refer S3C24x0's
-datasheet for further details. The macro #CALC_NFCONF_TIMING could help to
-calculate the register setting in a hardware independent manner.
-
- at note The regular NAND driver uses a platform data structure to define the
-NAND access timings.
-
- at note Its still possible to boot this image from NOR memory. If this routine
-detects it is running from NOR instead of the internal SRAM it skips any
-loading and returns immediately.
-
-*/
diff --git a/arch/arm/mach-samsung/lowlevel-s5pcxx.c b/arch/arm/mach-samsung/lowlevel-s5pcxx.c
deleted file mode 100644
index 15afa47ce3..0000000000
--- a/arch/arm/mach-samsung/lowlevel-s5pcxx.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- *
- * Based on code from u-boot found somewhere on the web
- * that seems to originate from Samsung
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <io.h>
-#include <init.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-clocks.h>
-#include <mach/s3c-generic.h>
-
-#ifdef CONFIG_S3C_PLL_INIT
-void  __bare_init s5p_init_pll(void)
-{
-    uint32_t reg;
-    int i;
-
-    /* Set Mux to FIN */
-    writel(0, S5P_CLK_SRC0);
-
-    writel(BOARD_APLL_LOCKTIME, S5P_xPLL_LOCK + S5P_APLL);
-
-    /* Disable PLL */
-    writel(0, S5P_xPLL_CON + S5P_APLL);
-    writel(0, S5P_xPLL_CON + S5P_MPLL);
-
-    /* Set up dividers */
-    reg = readl(S5P_CLK_DIV0);
-    reg &= ~(BOARD_CLK_DIV0_MASK);
-    reg |= (BOARD_CLK_DIV0_VAL);
-    writel(reg, S5P_CLK_DIV0);
-
-    /* Set up PLLs */
-    writel(BOARD_APLL_VAL, S5P_xPLL_CON + S5P_APLL);
-    writel(BOARD_MPLL_VAL, S5P_xPLL_CON + S5P_MPLL);
-    writel(BOARD_EPLL_VAL, S5P_xPLL_CON + S5P_EPLL);
-    writel(BOARD_VPLL_VAL, S5P_xPLL_CON + S5P_VPLL);
-
-    /* Wait for sync */
-    for (i = 0; i < 0x10000; ++i)
-        barrier();
-
-    reg = readl(S5P_CLK_SRC0);
-    reg |= 0x1111; /* switch MUX to PLL outputs */
-    writel(reg, S5P_CLK_SRC0);
-}
-#endif /* CONFIG_S3C_PLL_INIT */
diff --git a/arch/arm/mach-samsung/mem-s3c24x0.c b/arch/arm/mach-samsung/mem-s3c24x0.c
deleted file mode 100644
index 8d20f6d102..0000000000
--- a/arch/arm/mach-samsung/mem-s3c24x0.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-/**
- * @file
- * @brief Basic clock, sdram and timer handling for S3C24xx CPUs
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <linux/sizes.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-/**
- * Calculate the amount of connected and available memory
- * @return Memory size in bytes
- */
-uint32_t s3c24xx_get_memory_size(void)
-{
-	uint32_t reg, size;
-
-	/*
-	 * detect the current memory size
-	 */
-	reg = readl(S3C_BANKSIZE);
-
-	switch (reg & 0x7) {
-	case 0:
-		size = SZ_32M;
-		break;
-	case 1:
-		size = SZ_64M;
-		break;
-	case 2:
-		size = SZ_128M;
-		break;
-	case 4:
-		size = SZ_2M;
-		break;
-	case 5:
-		size = SZ_4M;
-		break;
-	case 6:
-		size = SZ_8M;
-		break;
-	default:
-		size = SZ_16M;
-		break;
-	}
-
-	/*
-	 * Is bank7 also configured for SDRAM usage?
-	 */
-	if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
-		size <<= 1;	/* also count this bank */
-
-	return size;
-}
-
-void s3c24xx_disable_second_sdram_bank(void)
-{
-	writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
-	writel(readl(S3C_MISCCR) | (1 << 18), S3C_MISCCR); /* disable its clock */
-}
diff --git a/arch/arm/mach-samsung/mem-s3c64xx.c b/arch/arm/mach-samsung/mem-s3c64xx.c
deleted file mode 100644
index c51245a378..0000000000
--- a/arch/arm/mach-samsung/mem-s3c64xx.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <errno.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-
-#define S3C_DRAMC_CHIP_0_CFG (S3C_DRAMC + 0x200)
-
-/* note: this routine honors the first memory bank only */
-unsigned s3c6410_get_memory_size(void)
-{
-	unsigned reg = readl(S3C_DRAMC_CHIP_0_CFG) & 0xff;
-
-	return ~(reg << 24) + 1;
-}
-
-/* configure the timing of one of the available external chip select lines */
-int s3c6410_setup_chipselect(int no, const struct s3c6410_chipselect *c)
-{
-	unsigned per_t = 1000000000 / s3c_get_hclk();
-	unsigned tacs, tcos, tacc, tcoh, tcah, shift;
-	uint32_t reg;
-
-	/* start of cycle to chip select assertion (= address/data setup) */
-	tacs = DIV_ROUND_UP(c->adr_setup_t, per_t);
-	/* start of CS to read/write assertion (= access setup) */
-	tcos = DIV_ROUND_UP(c->access_setup_t, per_t);
-	/* length of read/write assertion (= access length) */
-	tacc = DIV_ROUND_UP(c->access_t, per_t) - 1;
-	/* CS hold after access is finished */
-	tcoh = DIV_ROUND_UP(c->cs_hold_t, per_t);
-	/* adress/data hold after CS is deasserted */
-	tcah = DIV_ROUND_UP(c->adr_hold_t, per_t);
-
-	shift = no * 4;
-	reg = readl(S3C_SROM_BW) & ~(0xf << shift);
-	if (c->width == 16)
-		reg |= 0x1 << shift;
-	writel(reg, S3C_SROM_BW);
-#ifdef DEBUG
-	if (tacs > 15 || tcos > 15 || tacc > 31 || tcoh > 15 || tcah > 15) {
-		pr_err("At least one of the timings are invalid\n");
-		return -EINVAL;
-	}
-	pr_info("Will write 0x%08X\n", tacs << 28 | tcos << 24 | tacc << 16 |
-					tcoh << 12 | tcah << 8);
-#endif
-	writel(tacs << 28 | tcos << 24 | tacc << 16 | tcoh << 12 | tcah << 8,
-						S3C_SROM_BC0 + shift);
-
-	return 0;
-}
diff --git a/arch/arm/mach-samsung/mem-s5pcxx.c b/arch/arm/mach-samsung/mem-s5pcxx.c
deleted file mode 100644
index 943f691769..0000000000
--- a/arch/arm/mach-samsung/mem-s5pcxx.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- *
- * Based on code from u-boot found somewhere on the web
- * that seems to originate from Samsung
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <io.h>
-#include <init.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-iomap.h>
-
-#define S5P_DMC_CONCONTROL	0x00
-#define S5P_DMC_MEMCONTROL	0x04
-#define S5P_DMC_MEMCONFIG0	0x08
-#define S5P_DMC_MEMCONFIG1	0x0C
-#define S5P_DMC_DIRECTCMD	0x10
-#define S5P_DMC_PRECHCONFIG	0x14
-#define S5P_DMC_PHYCONTROL0	0x18
-#define S5P_DMC_PHYCONTROL1	0x1C
-#define S5P_DMC_PWRDNCONFIG	0x28
-#define S5P_DMC_TIMINGAREF	0x30
-#define S5P_DMC_TIMINGROW	0x34
-#define S5P_DMC_TIMINGDATA	0x38
-#define S5P_DMC_TIMINGPOWER	0x3C
-#define S5P_DMC_PHYSTATUS	0x40
-#define S5P_DMC_MRSTATUS	0x54
-
-/* DRAM commands */
-#define CMD(x)  ((x) << 24)
-#define BANK(x) ((x) << 16)
-#define CHIP(x) ((x) << 20)
-#define ADDR(x) (x)
-
-/**
- *  MR definition:
- *  1 11
- *  2 1098 7654 3210
- *      |     |  ^^^- burst length, 010=4, 011=8
- *      |     | ^- burst type 0=sequnential, 1=interleaved
- *      |   ^^^-- CAS latency
- *      |  ^----- test, 0=normal, 1=test
- *      |^---- DLL reset, 1=yes
- *    ^^^----- WR, 1=2, 2=3 etc.
- *  ^------- PD, 0=fast exit, 1=low power
- *
- *  EMR1 definition:
- *  1 11
- *  2 1098 7654 3210
- *         |       ^- DLL, 0=enable
- *         |      ^-- output strength, 0=full, 1=reduced
- *         |^.. .^--- Rtt, 00=off, 01=75, 10=150, 11=50 Ohm
- *         | ^^ ^-- Posted CAS# AL, 0-6
- *      ^^ ^------ OCD: 000=OCD exit, 111=enable defaults
- *     ^------ DQS#, 0=enable, 1=disable
- *    ^------- RDQS enable, 0=no, 1=yes
- *  ^-------- outputs, 0=enabled, 1=disabled
- *
- *  EMR2 definition:
- *  bit 7
- *  1 1
- *  2 1098 7654 3210
- *         ^-- SRT, 0=1x (0-85 deg.C), 1=2x (>85 deg.C)
- *  all other bits = 0
- *
- *  EMR3 definition: all bits 0
- */
-
-#define MRS	CMD(0x0)
-#define PALL	CMD(0x1)
-#define PRE	CMD(0x2)
-#define DPD	CMD(0x3)
-#define REFS	CMD(0x4)
-#define REFA	CMD(0x5)
-#define CKEL	CMD(0x6)
-#define NOP	CMD(0x7)
-#define REFSX	CMD(0x8)
-#define MRR	CMD(0x9)
-
-#define EMRS1 (MRS | BANK(1))
-#define EMRS2 (MRS | BANK(2))
-#define EMRS3 (MRS | BANK(3))
-
-/* Burst is (1 << S5P_DRAM_BURST), i.e. S5P_DRAM_BURST=2 for burst 4 */
-#ifndef S5P_DRAM_BURST
-/* (LP)DDR2 supports burst 4 only, make it default */
-# define S5P_DRAM_BURST 2
-#endif
-
-/**
- * Initialization sequences for different kinds of DRAM
- */
-#define dcmd(x) writel((x) | CHIP(chip), base + S5P_DMC_DIRECTCMD)
-
-static void __bare_init s5p_dram_init_seq_lpddr(phys_addr_t base, unsigned chip)
-{
-	const uint32_t emr = 0x400; /* DQS disable */
-	const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
-			  | ((S5P_DRAM_CAS) << 4)
-			  | (S5P_DRAM_BURST);
-	/* TODO this sequence is untested */
-	dcmd(PALL); dcmd(REFA); dcmd(REFA);
-	dcmd(MRS   | ADDR(mr));
-	dcmd(EMRS1 | ADDR(emr));
-}
-
-static void __bare_init s5p_dram_init_seq_lpddr2(phys_addr_t base, unsigned chip)
-{
-	const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
-			  | ((S5P_DRAM_CAS) << 4)
-			  | (S5P_DRAM_BURST);
-	/* TODO this sequence is untested */
-	dcmd(NOP);
-	dcmd(MRS | ADDR(mr));
-	do {
-		dcmd(MRR);
-	} while (readl(base + S5P_DMC_MRSTATUS) & 0x01); /* poll DAI */
-}
-
-static void __bare_init s5p_dram_init_seq_ddr2(phys_addr_t base, unsigned chip)
-{
-	const uint32_t emr = 0x400; /* DQS disable */
-	const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
-			  | ((S5P_DRAM_CAS) << 4)
-			  | (S5P_DRAM_BURST);
-	dcmd(NOP);
-	/* FIXME wait here? JEDEC recommends but nobody does */
-	dcmd(PALL); dcmd(EMRS2); dcmd(EMRS3);
-	dcmd(EMRS1 | ADDR(emr));         /* DQS disable */
-	dcmd(MRS   | ADDR(mr | 0x100));  /* DLL reset */
-	dcmd(PALL); dcmd(REFA); dcmd(REFA);
-	dcmd(MRS   | ADDR(mr));          /* DLL no reset */
-	dcmd(EMRS1 | ADDR(emr | 0x380)); /* OCD defaults */
-	dcmd(EMRS1 | ADDR(emr));         /* OCD exit */
-}
-
-#undef dcmd
-
-static inline void __bare_init s5p_dram_start_dll(phys_addr_t base, uint32_t phycon1)
-{
-	uint32_t pc0 = 0x00101000; /* the only legal initial value */
-	uint32_t lv;
-
-	/* Init DLL */
-	writel(pc0, base + S5P_DMC_PHYCONTROL0);
-	writel(phycon1, base + S5P_DMC_PHYCONTROL1);
-
-	/* DLL on */
-	pc0 |= 0x2;
-	writel(pc0, base + S5P_DMC_PHYCONTROL0);
-
-	/* DLL start */
-	pc0 |= 0x1;
-	writel(pc0, base + S5P_DMC_PHYCONTROL0);
-
-	/* Find lock val */
-	do {
-		lv = readl(base + S5P_DMC_PHYSTATUS);
-	} while ((lv & 0x7) != 0x7);
-
-	lv >>= 6;
-	lv &= 0xff; /* ctrl_lock_value[9:2] - coarse */
-	pc0 |= (lv << 24); /* ctrl_force */
-	writel(pc0, base + S5P_DMC_PHYCONTROL0); /* force value locking */
-}
-
-static inline void __bare_init s5p_dram_setup(phys_addr_t base, uint32_t mc0, uint32_t mc1,
-				       int bus16, uint32_t mcon)
-{
-	mcon |= (S5P_DRAM_BURST) << 20;
-	/* 16 or 32-bit bus ? */
-	mcon |= bus16 ? 0x1000 : 0x2000;
-	if (mc1)
-		mcon |= 0x10000; /* two chips */
-
-	writel(mcon, base + S5P_DMC_MEMCONTROL);
-
-	/* Set up memory layout */
-	writel(mc0, base + S5P_DMC_MEMCONFIG0);
-	if (mc1)
-		writel(mc1, base + S5P_DMC_MEMCONFIG1);
-
-	/* Open page precharge policy - reasonable defaults */
-	writel(0xFF000000, base + S5P_DMC_PRECHCONFIG);
-
-	/* Set up timings */
-	writel(DMC_TIMING_AREF, base + S5P_DMC_TIMINGAREF);
-	writel(DMC_TIMING_ROW,  base + S5P_DMC_TIMINGROW);
-	writel(DMC_TIMING_DATA, base + S5P_DMC_TIMINGDATA);
-	writel(DMC_TIMING_PWR,  base + S5P_DMC_TIMINGPOWER);
-}
-
-static inline void __bare_init s5p_dram_start(phys_addr_t base)
-{
-	/* Reasonable defaults and auto-refresh on */
-	writel(0x0FFF1070, base + S5P_DMC_CONCONTROL);
-	/* Reasonable defaults */
-	writel(0xFFFF00FF, base + S5P_DMC_PWRDNCONFIG);
-}
-
-/*
- * Initialize LPDDR memory bank
- * TODO: this function is untested, see also init_seq function
- */
-void __bare_init s5p_init_dram_bank_lpddr(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
-{
-	/* refcount 8, 90 deg. shift */
-	s5p_dram_start_dll(base, 0x00000085);
-	/* LPDDR type */
-	s5p_dram_setup(base, mc0, mc1, bus16, 0x100);
-
-	/* Start-Up Commands */
-	s5p_dram_init_seq_lpddr(base, 0);
-	if (mc1)
-		s5p_dram_init_seq_lpddr(base, 1);
-
-	s5p_dram_start(base);
-}
-
-/*
- * Initialize LPDDR2 memory bank
- * TODO: this function is untested, see also init_seq function
- */
-void __bare_init s5p_init_dram_bank_lpddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
-{
-	/* refcount 8, 90 deg. shift */
-	s5p_dram_start_dll(base, 0x00000085);
-	/* LPDDR2 type */
-	s5p_dram_setup(base, mc0, mc1, bus16, 0x200);
-
-	/* Start-Up Commands */
-	s5p_dram_init_seq_lpddr2(base, 0);
-	if (mc1)
-		s5p_dram_init_seq_lpddr2(base, 1);
-
-	s5p_dram_start(base);
-}
-
-/*
- * Initialize DDR2 memory bank
- */
-void __bare_init s5p_init_dram_bank_ddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
-{
-	/* refcount 8, 180 deg. shift */
-	s5p_dram_start_dll(base, 0x00000086);
-	/* DDR2 type */
-	s5p_dram_setup(base, mc0, mc1, bus16, 0x400);
-
-	/* Start-Up Commands */
-	s5p_dram_init_seq_ddr2(base, 0);
-	if (mc1)
-		s5p_dram_init_seq_ddr2(base, 1);
-
-	s5p_dram_start(base);
-}
-
-
-#define BANK_ENABLED(base) (readl((base) + S5P_DMC_PHYCONTROL0) & 1)
-#define NUM_EXTRA_CHIPS(base) ((readl((base) + S5P_DMC_MEMCONTROL) >> 16) & 0xF)
-
-#define BANK_START(x) ((x) & 0xFF000000)
-#define BANK_END(x) (BANK_START(x) | ~(((x) & 0x00FF0000) << 8))
-#define BANK_LEN(x) (BANK_END(x) - BANK_START(x) + 1)
-
-static inline void sortswap(uint32_t *x, uint32_t *y)
-{
-	if (*y < *x) {
-		*x ^= *y;
-		*y ^= *x;
-		*x ^= *y;
-	}
-}
-
-uint32_t s5p_get_memory_size(void)
-{
-	int i;
-	uint32_t len;
-	uint32_t mc[4] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
-	/* Read MEMCONFIG registers */
-	if (BANK_ENABLED(S5P_DMC0_BASE)) {
-		mc[0] = readl(S5P_DMC0_BASE + S5P_DMC_MEMCONFIG0);
-		if (NUM_EXTRA_CHIPS(S5P_DMC0_BASE) > 0)
-			mc[1] = readl(S5P_DMC0_BASE + S5P_DMC_MEMCONFIG1);
-	}
-	if (BANK_ENABLED(S5P_DMC1_BASE)) {
-		mc[2] = readl(S5P_DMC1_BASE + S5P_DMC_MEMCONFIG0);
-		if (NUM_EXTRA_CHIPS(S5P_DMC1_BASE) > 0)
-			mc[3] = readl(S5P_DMC1_BASE + S5P_DMC_MEMCONFIG1);
-	}
-	/* Sort using a sorting network */
-	sortswap(mc + 0, mc + 2);
-	sortswap(mc + 1, mc + 3);
-	sortswap(mc + 0, mc + 1);
-	sortswap(mc + 2, mc + 3);
-	sortswap(mc + 1, mc + 2);
-	/* Is at least one chip enabled? */
-	if (mc[0] == 0xFFFFFFFF)
-		return 0;
-	/* Determine maximum continuous region at start */
-	len = BANK_LEN(mc[0]);
-	for (i = 1; i < 4; ++i) {
-		if (BANK_START(mc[i]) == BANK_END(mc[i - 1]) + 1)
-			len += BANK_LEN(mc[i]);
-		else
-			break;
-	}
-	return len;
-}
diff --git a/arch/arm/mach-samsung/reset_source.c b/arch/arm/mach-samsung/reset_source.c
deleted file mode 100644
index c1365b2003..0000000000
--- a/arch/arm/mach-samsung/reset_source.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2012 Juergen Beisert - <kernel at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <init.h>
-#include <io.h>
-#include <reset_source.h>
-#include <mach/s3c-iomap.h>
-
-/* S3C2440 relevant */
-#define S3C2440_GSTATUS2 0xb4
-# define S3C2440_GSTATUS2_PWRST (1 << 0)
-# define S3C2440_GSTATUS2_SLEEPRST (1 << 1)
-# define S3C2440_GSTATUS2_WDRST (1 << 2)
-
-static int s3c_detect_reset_source(void)
-{
-	u32 reg = readl(S3C_GPIO_BASE + S3C2440_GSTATUS2);
-
-	if (reg & S3C2440_GSTATUS2_PWRST) {
-		reset_source_set(RESET_POR);
-		writel(S3C2440_GSTATUS2_PWRST,
-					S3C_GPIO_BASE + S3C2440_GSTATUS2);
-		return 0;
-	}
-
-	if (reg & S3C2440_GSTATUS2_SLEEPRST) {
-		reset_source_set(RESET_WKE);
-		writel(S3C2440_GSTATUS2_SLEEPRST,
-					S3C_GPIO_BASE + S3C2440_GSTATUS2);
-		return 0;
-	}
-
-	if (reg & S3C2440_GSTATUS2_WDRST) {
-		reset_source_set(RESET_WDG);
-		writel(S3C2440_GSTATUS2_WDRST,
-					S3C_GPIO_BASE + S3C2440_GSTATUS2);
-		return 0;
-	}
-
-	/* else keep the default 'unknown' state */
-	return 0;
-}
-
-device_initcall(s3c_detect_reset_source);
diff --git a/arch/arm/mach-samsung/s3c-timer.c b/arch/arm/mach-samsung/s3c-timer.c
deleted file mode 100644
index 38bcebc7c4..0000000000
--- a/arch/arm/mach-samsung/s3c-timer.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-
-#define S3C_TCFG0 (S3C_TIMER_BASE + 0x00)
-# define S3C_TCFG0_T4MASK 0xff00
-# define S3C_TCFG0_SET_PSCL234(x) ((x) << 8)
-# define S3C_TCFG0_GET_PSCL234(x) (((x) >> 8) & 0xff)
-#define S3C_TCFG1 (S3C_TIMER_BASE + 0x04)
-# define S3C_TCFG1_T4MASK 0xf0000
-# define S3C_TCFG1_SET_T4MUX(x) ((x) << 16)
-# define S3C_TCFG1_GET_T4MUX(x) (((x) >> 16) & 0xf)
-#define S3C_TCON (S3C_TIMER_BASE + 0x08)
-# define S3C_TCON_T4MASK (7 << 20)
-# define S3C_TCON_T4START (1 << 20)
-# define S3C_TCON_T4MANUALUPD (1 << 21)
-# define S3C_TCON_T4RELOAD (1 <<22)
-#define S3C_TCNTB4 (S3C_TIMER_BASE + 0x3c)
-#define S3C_TCNTO4 (S3C_TIMER_BASE + 0x40)
-
-#ifdef CONFIG_ARCH_S3C24xx
-# define TIMER_WIDTH 16
-# define TIMER_SHIFT 10
-# define PRE_MUX 3
-# define PRE_MUX_ADD 1
-static const uint32_t max = 0x0000ffff;
-#else /* for S3C64xx and S5Pxx */
-# define TIMER_WIDTH 32
-# define TIMER_SHIFT 10
-# define PRE_MUX 4
-# define PRE_MUX_ADD 0
-static const uint32_t max = ~0;
-#endif
-
-static void s3c_init_t4_clk_source(void)
-{
-	unsigned reg;
-
-	reg = readl(S3C_TCON) & ~S3C_TCON_T4MASK; /* stop timer 4 */
-	writel(reg, S3C_TCON);
-	reg = readl(S3C_TCFG0) & ~S3C_TCFG0_T4MASK;
-	reg |= S3C_TCFG0_SET_PSCL234(0); /* 0 means pre scaler is '256' */
-	writel(reg, S3C_TCFG0);
-	reg = readl(S3C_TCFG1) & ~S3C_TCFG1_T4MASK;
-	reg |= S3C_TCFG1_SET_T4MUX(PRE_MUX); /* / 16 */
-	writel(reg, S3C_TCFG1);
-}
-
-static unsigned s3c_get_t4_clk(void)
-{
-	unsigned clk = s3c_get_pclk();
-	unsigned pre = S3C_TCFG0_GET_PSCL234(readl(S3C_TCFG0)) + 1;
-	unsigned div = S3C_TCFG1_GET_T4MUX(readl(S3C_TCFG1)) + PRE_MUX_ADD;
-
-	return clk / pre / (1 << div);
-}
-
-static void s3c_timer_init(void)
-{
-	unsigned tcon;
-
-	tcon = readl(S3C_TCON) & ~S3C_TCON_T4MASK;
-
-	writel(max, S3C_TCNTB4);	/* reload value */
-	/* force a manual counter update */
-	writel(tcon | S3C_TCON_T4MANUALUPD, S3C_TCON);
-}
-
-static void s3c_timer_start(void)
-{
-	unsigned tcon;
-
-	tcon  = readl(S3C_TCON) & ~S3C_TCON_T4MANUALUPD;
-	tcon |= S3C_TCON_T4START | S3C_TCON_T4RELOAD;
-	writel(tcon, S3C_TCON);
-}
-
-static uint64_t s3c_clocksource_read(void)
-{
-	/* note: its a down counter */
-	return max - readl(S3C_TCNTO4);
-}
-
-static struct clocksource cs = {
-	.read = s3c_clocksource_read,
-	.mask = CLOCKSOURCE_MASK(TIMER_WIDTH),
-	.shift = TIMER_SHIFT,
-	.priority = 80,
-};
-
-static int s3c_clk_src_init(void)
-{
-	/* select its clock source first */
-	s3c_init_t4_clk_source();
-
-	s3c_timer_init();
-	s3c_timer_start();
-
-	cs.mult = clocksource_hz2mult(s3c_get_t4_clk(), cs.shift);
-
-	return init_clock(&cs);
-}
-core_initcall(s3c_clk_src_init);
diff --git a/scripts/.gitignore b/scripts/.gitignore
index f78793eab7..3ca742ac6e 100644
--- a/scripts/.gitignore
+++ b/scripts/.gitignore
@@ -14,7 +14,6 @@ kwboot-target
 gen_netx_image
 omap_signGP
 mk-omap-image
-s5p_cksum
 mkublheader
 zynq_mkimage
 socfpga_mkimage
diff --git a/scripts/Kconfig b/scripts/Kconfig
index 25d57e4b2a..dcd5f32d1d 100644
--- a/scripts/Kconfig
+++ b/scripts/Kconfig
@@ -63,13 +63,6 @@ config OMAP_IMAGE
 	help
 	  This enables building the image creation tools for TI OMAP SoCs
 
-config S5P_IMAGE
-	bool "S5P image tool" if COMPILE_HOST_TOOLS
-	depends on ARCH_S5PCxx || COMPILE_HOST_TOOLS
-	default y if ARCH_S5PCxx
-	help
-	  This enables building the image creation tool for S5P SoCs
-
 config DAVINCI_IMAGE
 	bool "Davinci image tool" if COMPILE_HOST_TOOLS
 	depends on ARCH_DAVINCI || COMPILE_HOST_TOOLS
diff --git a/scripts/Makefile b/scripts/Makefile
index 39d71d4e99..ac88ebb240 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -19,7 +19,6 @@ hostprogs-always-$(CONFIG_KALLSYMS)			+= kallsyms
 hostprogs-always-$(CONFIG_MIPS)				+= mips-relocs
 hostprogs-always-$(CONFIG_MVEBU_HOSTTOOLS)		+= kwbimage kwboot mvebuimg
 hostprogs-always-$(CONFIG_OMAP_IMAGE)			+= omap_signGP mk-omap-image
-hostprogs-always-$(CONFIG_S5P_IMAGE)			+= s5p_cksum
 hostprogs-always-$(CONFIG_DAVINCI_IMAGE)		+= mkublheader
 HOSTCFLAGS_zynq_mkimage.o = -I$(srctree) -I$(srctree)/arch/arm/mach-zynq/include
 hostprogs-always-$(CONFIG_ZYNQ_MKIMAGE)			+= zynq_mkimage
-- 
2.30.2




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