[PATCH v1 2/2] net: phy: micrel: port clock select support

[Trent Piepho]

On Wed, Oct 13, 2021 at 3:23 AM Oleksij Rempel <o.rempel at pengutronix.de> wrote:
>
> On Wed, Oct 13, 2021 at 01:48:20AM -0700, Trent Piepho wrote:
> > On Wed, Oct 13, 2021 at 12:29 AM Oleksij Rempel <o.rempel at pengutronix.de> wrote:
> > > > Note that not just KSZ8081 has this bit.  Also KSZ8021, KSZ8031, and
> > > > KSZ8051, which has the existing different method to handle it, as
> > > > described earlier.
> > >
> > > ok, i'll sync all of this PHYs with the state of the kernel driver.
> > > The board fixups should be removed by someone who can confirm it.
> >
> > If you copy the entire kernel driver you will massively bloat this
> > code with stuff that is totally unused.
>
> Yes.

Can you get network support into a Barebox that fits in IMX8 OCRAM?
Bloat matters. There are things barebox can not do anymore because it
has grown too large.

> > > > > +static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
> > > > > +{
> > > > > +       int ctrl;
> > > > > +
> > > > > +       ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
> > > > > +       if (ctrl < 0)
> > > > > +               return ctrl;
> > > > > +
> > > > > +       if (val)
> > > > > +               ctrl |= KSZPHY_RMII_REF_CLK_SEL;
> > > > > +       else
> > > > > +               ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
> > > > > +
> > > > > +       return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
> > > > > +}
> > > >
> > > > phy_set_bits(phydev, MII_KSZPHY_CTRL, KSZ8051_RMII_50MHZ_CLK);
> > >
> > > No, it should be synced with kernel not in the opposite way.
> >
> > If you want the code to match, then improve the kernel code rather
> > than make Barebox code worse.  phy_set_bits, phy_clear_bits and
> > phy_modify exist.  One can not use them if a kernel driver has not
> > been refactored to use them?
>
> Sure. Can you please show example of the kszphy_rmii_clk_sel() refactoring.
> And how much optimization will it introduce? Please compared with disassembled
> part.

struct kszphy_priv *priv = phydev->priv;
if (priv->set_rmii_clk_sel)
    phy_set_bits(phydev, MII_KSZPHY_CTRL, KSZ8051_RMII_50MHZ_CLK);

But did you really need me to provide that example?