[PATCH 2/2] RISC-V: extend multi-image to support both S- and M-Mode
a.fatoum at pengutronix.de
Tue May 11 04:26:35 PDT 2021
On 11.05.21 13:11, Antony Pavlov wrote:
> On Tue, 11 May 2021 08:41:44 +0200
> Ahmad Fatoum <a.fatoum at pengutronix.de> wrote:
>> We can't currently mix S-Mode and M-Mode images in the same build
>> and there's no straight-forward way to determine which mode we are in.
>> Move the decision on which mode barebox is targeted at out of Kconfig
>> and into the PBL. PBL code can call either barebox_riscv_supervisor_entry
>> or barebox_riscv_machine_entry to signal to barebox proper which mode
>> it's running in.
> It looks like this comment is slightly outdated.
> There is neither barebox_riscv_supervisor_entry nor barebox_riscv_machine_entry
> inside the patch.
barebox_riscv_machine_entry is defined and used once for Erizo.
barebox_riscv_supervisor_entry is defined and used twice, once for HiFive
and another for the generic image (used for virt).
>> Currently the only user of this information is the
>> RISC-V timer clocksource driver.
> Please add necessary mode check to the sbi_init() from arch/riscv/lib/sbi.c too.
Yes, I should. Will send fixup later.
>> Any new code that does IS_ENABLED(CONFIG_RISCV_SBI) or
>> IS_ENABLED(CONFIG_RISCV_M_MODE) should also be adapted to use riscv_mode().
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