[PATCH v2 02/11] RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive

[Antony Pavlov]

On Fri, 7 May 2021 16:44:24 +0200
Ahmad Fatoum <a.fatoum at pengutronix.de> wrote:

Hi Ahmad !

> Hello Antony,
> 
> On 07.05.21 16:25, Antony Pavlov wrote:
> >> I would really like to have a riscv{32,64}_defconfig that can just build all boards
> >> at once. Do you know if this could be dynamically determined?
> > 
> > At the moment I have not answer.
> > I'll try to investigate dynamic mode determination, it's very attractive idea.
> > 
> > On the other hand compile time mode selection is not the show stopper for
> > "one defconfig to build them all": we have to make STACK_SIZE and MALLOC_SIZE
> > per-board parameters not per-defconfig parameters like now.
> > 
> > If we could make STACK_SIZE and MALLOC_SIZE per-board compile-time parameters then
> > we can make RISC-V mode per-board compile-time parameter too. Is this solution
> > acceptable?
> 
> MALLOC_SIZE can be set as 0 and barebox will determine it based on
> membase + memsize that are set by PBL.
> 
> STACK_SIZE must be set per Kconfig, but I think even a generous default stack
> size should accommodate all targets.
> 
> If we do the same for RISC-V mode that would probably mean having
> two functions barebox_riscv_machine_entry() and barebox_riscv_supervisor_entry()
> in PBL that take care to pass the correct info to barebox proper.
> 
> Apparently, you can determine mode if you catch exceptions:
> https://forums.sifive.com/t/how-to-determine-the-current-execution-privilege-mode/2823

Hmm, answer is mostly negative:

<<
  RISC-V deliberately doesn’t make it easy for code to discover
  what mode it is running it because this is a virtualisation hole.
  As a general principle, code should be designed for and implicitly
  know what mode it will run in. 
>>

> We don't yet install exception handlers in barebox, but I am fine with using
> different PBL common code entry functions.
> 
> What do you think?

I think that adding exception handling to barebox would be very handy.
At the moment barebox sometimes hangs during my experiments without any error message.
Even with a simple exception handler that just prints out epc, status and cause registers
I have much more information on hang reason.

-- 
Best regards,
  Antony Pavlov

 
> > 
> >>> +
> >>>  source "arch/riscv/Kconfig.socs"
> >>>  
> >>>  config CPU_SUPPORTS_32BIT_KERNEL
> >>> @@ -97,14 +109,4 @@ config NMON_HELP
> >>>  	  Say yes here to get the nmon commands message on
> >>>  	  every nmon start.
> >>>  
> >>> -# set if we run in machine mode, cleared if we run in supervisor mode
> >>> -config RISCV_M_MODE
> >>> -	bool
> >>> -
> >>> -# set if we are running in S-mode and can use SBI calls
> >>> -config RISCV_SBI
> >>> -	bool
> >>> -	depends on !RISCV_M_MODE
> >>> -	default y
> >>> -
> >>>  endmenu
> >>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> >>> index c6875738d0..f767942f34 100644
> >>> --- a/arch/riscv/Kconfig.socs
> >>> +++ b/arch/riscv/Kconfig.socs
> >>> @@ -3,10 +3,10 @@ menu "SoC selection"
> >>>  config SOC_ERIZO
> >>>  	bool "Erizo SoC"
> >>>  	depends on ARCH_RV32I
> >>> +	depends on RISCV_M_MODE
> >>>  	select HAS_ASM_DEBUG_LL
> >>>  	select HAS_NMON
> >>>  	select USE_COMPRESSED_DTB
> >>> -	select RISCV_M_MODE
> >>>  	select RISCV_TIMER
> >>>  
> >>>  config BOARD_ERIZO_GENERIC
> >>> @@ -15,6 +15,7 @@ config BOARD_ERIZO_GENERIC
> >>>  
> >>>  config SOC_VIRT
> >>>  	bool "QEMU Virt Machine"
> >>> +	depends on RISCV_SBI
> >>>  	select BOARD_RISCV_GENERIC_DT
> >>>  	select CLINT_TIMER
> >>>  	help
> >>> @@ -23,6 +24,7 @@ config SOC_VIRT
> >>>  
> >>>  config SOC_SIFIVE
> >>>  	bool "SiFive SoCs"
> >>> +	depends on RISCV_SBI
> >>>  	select CLK_SIFIVE
> >>>  	select CLK_SIFIVE_PRCI
> >>>  	select RISCV_TIMER
> >>> diff --git a/arch/riscv/configs/erizo_generic_defconfig b/arch/riscv/configs/erizo_generic_defconfig
> >>> index 247a179130..16168eef66 100644
> >>> --- a/arch/riscv/configs/erizo_generic_defconfig
> >>> +++ b/arch/riscv/configs/erizo_generic_defconfig
> >>> @@ -1,3 +1,4 @@
> >>> +CONFIG_RISCV_M_MODE=y
> >>>  CONFIG_SOC_ERIZO=y
> >>>  # CONFIG_GLOBALVAR is not set
> >>>  CONFIG_STACK_SIZE=0x20000
> >>>
> >>
> >> -- 
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> > 
> > 
> 
> -- 
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |