[PATCH 7/9] RISC-V: add initial LiteX SoC support

[Jan Lübbe]

On Wed, 2021-05-05 at 13:08 +0300, Antony Pavlov wrote:
> LiteX is a Migen-based System on Chip, supporting softcore
> VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
> 
> See https://github.com/enjoy-digital/litex and
> https://github.com/litex-hub/linux-on-litex-vexriscv
> for details.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> ---
> 
> 


> +config MACH_LITEX
> +	bool "litex family"
> +	select ARCH_RV32I
> +	select HAS_DEBUG_LL
> +	select HAS_NMON
> +	select USE_COMPRESSED_DTB
> +	select RISCV_SBI
> +


Hmm, there is also https://github.com/litex-hub/linux-on-litex-rocket/ which
uses the 64-bit RocketChip CPU. How would that fit into this naming scheme?
Would it be a different MACH?

> +/dts-v1/;
> +
> +/ {
> +	compatible = "litex,vexriscv-soc-linux";
> +
> +	#address-cells = <1>;
> 

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