[PATCH 2/3] RISC-V: asm: barebox-riscv-head: use load-offset of 0

[Ahmad Fatoum]

Incoming RISC-V bootm implementation will use the same bootm handler for
booting both kernel and barebox. For this to work, the load offset in
the header needs to make sense. As non-generic DT barebox images have
enough knowledge about the platform to know where to place the stack,
they don't require a load offset, thus set it to zero.

Signed-off-by: Ahmad Fatoum <ahmad at a3f.at>
Signed-off-by: Ahmad Fatoum <a.fatoum at pengutronix.de>
---
 arch/riscv/include/asm/barebox-riscv-head.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/barebox-riscv-head.h b/arch/riscv/include/asm/barebox-riscv-head.h
index f681ec8bcee6..a4c33472cd53 100644
--- a/arch/riscv/include/asm/barebox-riscv-head.h
+++ b/arch/riscv/include/asm/barebox-riscv-head.h
@@ -30,7 +30,7 @@
 
 #ifndef __barebox_riscv_head
 #define __barebox_riscv_head() \
-	__barebox_riscv_header("nop", 0x55555555FFFFFFFF, 0x0, "barebox", "RSCV")
+	__barebox_riscv_header("nop", 0x0, 0x0, "barebox", "RSCV")
 #endif
 
 #endif /* __ASM_RISCV_HEAD_H */
-- 
2.29.2