[PATCH] Arm: i.MX5: Do not disable L2 cache

[Sascha Hauer]

On Thu, Jun 18, 2020 at 02:21:08PM +0200, Lucas Stach wrote:
> Am Donnerstag, den 18.06.2020, 14:12 +0200 schrieb Sascha Hauer:
> > Disabling the L2 cache is not working in imx5_init_lowlevel() because
> > the necessary cache maintenance operations are missing. This often
> > results in cache corruption in a chainloaded barebox.
> > Disabling the cache is unnecessary: when we come from the ROM the L2
> > cache is disabled anyway, so disabling it is a no-op. When we get here
> > in a chainloaded barebox the L2 cache is already enabled and correctly
> > configured. So instead of initializing it again we can take an enabled
> > L2 cache as a sign to skip initialization and just return from the
> > function.
> 
> While this won't hurt much, shouldn't we also disable the L2 cache on
> Barebox shutdown, like we do on other SoCs?

Documentation/arm/booting.rst clearly states:

Data cache must be off.

So yes, to do it correctly we should disable the L2 cache.

So far I am happy that my QSB board no longer randomly crashes in a
secondary barebox.

Sascha

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