[PATCH] PPC: request a consistent memory layout (part II)

[Sascha Hauer]

On Mon, May 22, 2017 at 12:34:38PM +0200, Juergen Borleis wrote:
> Hi Sascha,
> 
> On Monday 22 May 2017 12:26:43 Sascha Hauer wrote:
> > [...]
> > I have the feeling that we should actively put the vector table to one
> > of the two locations, so we should implicitly know where it is and not
> > have to test the MSR_IP bit.
> 
> Sometimes it depends on the boot mode. You can locate the NOR flash memory 
> at 0x00000 or 0xfff00000 (via bootstrap pins) and in the latter case the 
> vector table is at 0xfff00000 (at least the reset vector)!

Regardless of the bootmode in the end the vector table should be in
SDRAM, no? With a vector table in flash no vector except the reset
vector will point to a valid address and thus we won't be able to catch
any exceptions. Looing at the powerpc code we really do have exception
handling code, but I don't know how broken it actually is.

Sascha

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