[PATCH v2 5/8] ARM: socfpga: add arria10 support
Sascha Hauer
s.hauer at pengutronix.de
Wed May 3 04:52:17 PDT 2017
On Wed, May 03, 2017 at 01:49:51PM +0200, Sascha Hauer wrote:
> On Fri, Apr 28, 2017 at 04:41:41PM +0200, Steffen Trumtrar wrote:
> > Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that
> > is already supported in barebox.
> > Both a the same in some parts, but totaly different in
> > others. Most of the hardware blocks are the same in the
> > SoC parts. The OCRAM is larger on the Arria10 and the
> > SDRAM controller is different.
> > The serial core only supports 32bit accesses (different to
> > the 8bit accesses on the Cyclone5).
> >
> > As Arria10 has 256KB of OCRAM, it is possible to fit a larger
> > barebox (and/or use PBL) instead of the two stage bootprocess
> > used on the Cyclone5 and its 64KB OCRAM.
> >
> > Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
> > ---
> > arch/arm/Kconfig | 6 +-
> > arch/arm/mach-socfpga/Kconfig | 19 +-
> > arch/arm/mach-socfpga/Makefile | 10 +-
> > arch/arm/mach-socfpga/arria10-bootsource.c | 53 +-
> > arch/arm/mach-socfpga/arria10-clock-manager.c | 815 +++++++-
> > arch/arm/mach-socfpga/arria10-generic.c | 85 +-
> > arch/arm/mach-socfpga/arria10-init.c | 193 ++-
> > arch/arm/mach-socfpga/arria10-reset-manager.c | 398 +++-
> > arch/arm/mach-socfpga/arria10-sdram.c | 535 +++++-
> > arch/arm/mach-socfpga/cyclone5-bootsource.c | 45 +-
>
> This does not apply. arch/arm/mach-socfpga/cyclone5-bootsource.c is
> modified here but does not exist in my tree.
Forget this. Patch 1/8 did not make it to the list. I used this from the
v1 series.
Sascha
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