[PATCH v2] ARM: imx6: reset PLL2's PFD2 on i.MX6D

[Uwe Kleine-König]

The check for is_imx6q was introduced initially in

	f1f6d76370b3 ("ARM: i.MX6: correct work flow of PFDs from uboot-sources")

to differentiate between i.MX6DL+i.MX6SL and i.MX6Q. The i.MX6D must be
handled like the latter, so drop the check. i.MX6DL+i.MX6SL can be
ignored here since since

	a66596282413 ("imx6: lowlevel_init: Fix workaround for new i.MX6s chips")

the PFD handling is only done for i.MX6DQ.

Update the comment to be not only logically correct but also helpful.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index ba8fb8964ac8..18509a7b51db 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -65,10 +65,10 @@ void imx6_init_lowlevel(void)
 	writel(0xffffffff, 0x020c407c);
 	writel(0xffffffff, 0x020c4080);
 
-	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
-	 * to make sure PFD is working right, otherwise, PFDs may
-	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
-	 * workaround in ROM code, as bus clock need it
+	/*
+	 * Due to a hardware bug (related to errata ERR006282) on i.MX6DQ we
+	 * need to gate/ungate all PFDs to make sure PFD is working right,
+	 * otherwise PFDs may not output clock after reset.
 	 */
 	if (is_imx6q || is_imx6d) {
 		writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
@@ -77,7 +77,7 @@ void imx6_init_lowlevel(void)
 		       BM_ANADIG_PFD_480_PFD0_CLKGATE,
 		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
 		writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
-		       (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+		       BM_ANADIG_PFD_528_PFD2_CLKGATE |
 		       BM_ANADIG_PFD_528_PFD1_CLKGATE |
 		       BM_ANADIG_PFD_528_PFD0_CLKGATE,
 		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
@@ -88,7 +88,7 @@ void imx6_init_lowlevel(void)
 		       BM_ANADIG_PFD_480_PFD0_CLKGATE,
 		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
 		writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
-		       (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+		       BM_ANADIG_PFD_528_PFD2_CLKGATE |
 		       BM_ANADIG_PFD_528_PFD1_CLKGATE |
 		       BM_ANADIG_PFD_528_PFD0_CLKGATE,
 		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
-- 
2.8.1