[PATCH 1/2] nand: imx6: Changed default NAND clock

[Sascha Hauer]

On Thu, Oct 20, 2016 at 03:40:06PM +0200, Christian Hemp wrote:
> From: Daniel Schultz <d.schultz at phytec.de>
> 
> The Barebox recognized false bad erase blocks while booting from a
> Spansion NAND (1). This error occurred due a to high clock. The
> Kernel sets the default NAND clock to 22Mhz. So, to fix this error and
> to be more identical with the Kernel, the Barebox should be too.

The timing is changed afterwards to a faster mode and the clock is
changed again. Does that work for you properly?

Sascha

> 
> 1: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion
> S34ML08G2), 1024MiB, page size: 2048, OOB size: 128
> 
> Signed-off-by: Daniel Schultz <d.schultz at phytec.de>
> Tested-by: Stefan Lengfeld <s.lengfeld at phytec.de>
> Signed-off-by: Christian Hemp <c.hemp at phytec.de>
> ---
>  drivers/mtd/nand/nand_mxs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
> index 01aa063..fe955e8 100644
> --- a/drivers/mtd/nand/nand_mxs.c
> +++ b/drivers/mtd/nand/nand_mxs.c
> @@ -2145,7 +2145,7 @@ static int mxs_nand_probe(struct device_d *dev)
>  
>  	if (mxs_nand_is_imx6(nand_info)) {
>  		clk_disable(nand_info->clk);
> -		clk_set_rate(nand_info->clk, 96000000);
> +		clk_set_rate(nand_info->clk, 22000000);
>  		clk_enable(nand_info->clk);
>  		nand_info->dma_channel_base = 0;
>  	} else {
> -- 
> 1.9.1
> 
> 
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