[PATCH] imx6-mmdc: fix automatic power down enable in write level calibration
Eric Nelson
eric at nelint.com
Mon Oct 26 07:07:32 PDT 2015
Hi Sascha,
On 10/25/2015 11:53 PM, Sascha Hauer wrote:
> Hi Eric,
>
> On Fri, Oct 23, 2015 at 12:49:44PM -0700, Eric Nelson wrote:
>> Bit 0 of the MAPSR register controls auto power down.
>>
>> Explicitly clear this bit instead of reserved bit when
>> exiting from mmdc_do_write_level_calibration().
>>
>> Signed-off-by: Eric Nelson <eric at nelint.com>
>
> Looks good, applied. Did this bug have any practical impacts?
>
I found the mistake when reviewing the code and didn't run it.
>From the manual, bit 3 is listed as reserved with a default
value of zero, so that should have no effect.
Not clearing bit zero should only prevent the MMDC from
invoking self-refresh.
>From the RM:
Automatic Power Saving Disable. When the value of PSD is
"0" (i.e automatic power saving is enabled) then the PST is
activated and MMDC will enter automatically to self-refresh
while the number of idle cycle reached.
I'm reviewing this code for possible inclusion into a U-Boot
SPL-based DDR calibration routine and haven't run it.
> Sascha
>
>> ---
>> arch/arm/mach-imx/imx6-mmdc.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
>> index 64fb624..40fe0cf 100644
>> --- a/arch/arm/mach-imx/imx6-mmdc.c
>> +++ b/arch/arm/mach-imx/imx6-mmdc.c
>> @@ -103,9 +103,9 @@ int mmdc_do_write_level_calibration(void)
>> val |= 0x00005500;
>> writel(val, (P0_IPS + MDPDC));
>>
>> - /* enable Adopt power down timer: */
>> + /* enable auto power down timer: */
>> val = readl(P0_IPS + MAPSR);
>> - val &= 0xfffffff7;
>> + val &= ~1;
>> writel(val, (P0_IPS + MAPSR));
>>
>> /* clear CON_REQ */
>> --
>> 2.6.2
>>
>>
>
More information about the barebox
mailing list