[PATCH 1/3] mxs: iomux-imx28: Fix keeper/pullup/drive strength/voltage flags
Uwe Kleine-König
u.kleine-koenig at pengutronix.de
Thu Oct 23 15:45:59 PDT 2014
Double check all pin's BK, PE, SE and VE flags and correct wrong
definitions using i.MX28 Applications Processor Reference Manual, Rev 2,
08/2013.
Fixes: b1df39c28c7f (mxs: Add remaining i.MX28 iomux configurations)
Fixes: e2cee7cb6790 (mxs: add support for mx28-evk)
Fixes: 03e61e1bd967 (STM378x: Add i.MX28 architecture)
Signed-off-by: Uwe Kleine-König <u.kleine-koenig at pengutronix.de>
---
arch/arm/mach-mxs/include/mach/iomux-imx28.h | 52 ++++++++++++++--------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-mxs/include/mach/iomux-imx28.h b/arch/arm/mach-mxs/include/mach/iomux-imx28.h
index 82918cf851b1..c9ab8a93aea2 100644
--- a/arch/arm/mach-mxs/include/mach/iomux-imx28.h
+++ b/arch/arm/mach-mxs/include/mach/iomux-imx28.h
@@ -268,9 +268,9 @@
#define SSP3_CMD_ENET1_1588_EVENT0_IN (FUNC(2) | PORTF(2, 25) | SE | VE | PE)
#define SSP3_CMD_GPIO (FUNC(3) | PORTF(2, 25) | SE | VE | PE)
#define SSP3_SCK (FUNC(0) | PORTF(2, 24) | SE | VE | PE)
-#define SSP3_SCK_AUART4_TX (FUNC(1) | PORTF(2, 24) | SE | VE | PE)
-#define SSP3_SCK_ENET1_1588_EVENT0_OUT (FUNC(2) | PORTF(2, 24) | SE | VE | PE)
-#define SSP3_SCK_GPIO (FUNC(3) | PORTF(2, 24) | SE | VE | PE)
+#define SSP3_SCK_AUART4_TX (FUNC(1) | PORTF(2, 24) | SE | VE | BK)
+#define SSP3_SCK_ENET1_1588_EVENT0_OUT (FUNC(2) | PORTF(2, 24) | SE | VE | BK)
+#define SSP3_SCK_GPIO (FUNC(3) | PORTF(2, 24) | SE | VE | BK)
#define SSP2_D5 (FUNC(0) | PORTF(2, 21) | SE | VE | PE)
#define SSP2_D5_SSP2_D2 (FUNC(1) | PORTF(2, 21) | SE | VE | PE)
#define SSP2_D5_USB0_OC (FUNC(2) | PORTF(2, 21) | SE | VE | PE)
@@ -291,9 +291,9 @@
#define SSP2_CMD_AUART2_TX (FUNC(1) | PORTF(2, 17) | SE | VE | PE)
#define SSP2_CMD_SAIF0_SDATA2 (FUNC(2) | PORTF(2, 17) | SE | VE | PE)
#define SSP2_CMD_GPIO (FUNC(3) | PORTF(2, 17) | SE | VE | PE)
-#define SSP2_SCK (FUNC(0) | PORTF(2, 16) | SE | VE | PE)
-#define SSP2_SCK_AUART2_RX (FUNC(1) | PORTF(2, 16) | SE | VE | PE)
-#define SSP2_SCK_SAIF0_SDATA1 (FUNC(2) | PORTF(2, 16) | SE | VE | PE)
+#define SSP2_SCK (FUNC(0) | PORTF(2, 16) | SE | VE | BK)
+#define SSP2_SCK_AUART2_RX (FUNC(1) | PORTF(2, 16) | SE | VE | BK)
+#define SSP2_SCK_SAIF0_SDATA1 (FUNC(2) | PORTF(2, 16) | SE | VE | BK)
#define SSP2_SCK_GPIO (FUNC(3) | PORTF(2, 16) | SE | VE | PE)
#define SSP1_D3 (FUNC(0) | PORTF(2, 15) | SE | VE | PE)
#define SSP1_D3_SSP2_D7 (FUNC(1) | PORTF(2, 15) | SE | VE | PE)
@@ -339,13 +339,13 @@
#define SSP0_D0_GPIO (FUNC(3) | PORTF(2, 0) | SE | VE | PE)
/* Bank 3, GPIO pins 96 ... 127 */
-#define LCD_RESET (FUNC(0) | PORTF(3, 30))
-#define LCD_RESET_LCD_VSYNC (FUNC(1) | PORTF(3, 30))
-#define LCD_RESET_GPIO (FUNC(3) | PORTF(3, 30))
-#define PWM4 (FUNC(0) | PORTF(3, 29))
-#define PWM4_GPIO (FUNC(3) | PORTF(3, 29))
-#define PWM3 (FUNC(0) | PORTF(3, 28))
-#define PWM3_GPIO (FUNC(3) | PORTF(3, 28))
+#define LCD_RESET (FUNC(0) | PORTF(3, 30) | SE | VE | BK)
+#define LCD_RESET_LCD_VSYNC (FUNC(1) | PORTF(3, 30) | SE | VE | BK)
+#define LCD_RESET_GPIO (FUNC(3) | PORTF(3, 30) | SE | VE | BK)
+#define PWM4 (FUNC(0) | PORTF(3, 29) | SE | VE | BK)
+#define PWM4_GPIO (FUNC(3) | PORTF(3, 29) | SE | VE | BK)
+#define PWM3 (FUNC(0) | PORTF(3, 28) | SE | VE | BK)
+#define PWM3_GPIO (FUNC(3) | PORTF(3, 28) | SE | VE | BK)
#define SPDIF_TX (FUNC(0) | PORTF(3, 27) | SE | VE | BK)
#define SPDIF_TX_ENET1_RX_ER (FUNC(2) | PORTF(3, 27) | SE | VE | BK)
#define SPDIF_TX_GPIO (FUNC(3) | PORTF(3, 27) | SE | VE | BK)
@@ -377,23 +377,23 @@
#define SAIF0_MCLK_PWM3 (FUNC(1) | PORTF(3, 20) | SE | VE | BK)
#define SAIF0_MCLK_AUART4_CTS (FUNC(2) | PORTF(3, 20) | SE | VE | BK)
#define SAIF0_MCLK_GPIO (FUNC(3) | PORTF(3, 20) | SE | VE | BK)
-#define PWM2 (FUNC(0) | PORTF(3, 18))
-#define PWM2_USB0_ID (FUNC(1) | PORTF(3, 18))
-#define PWM2_USB1_OC (FUNC(2) | PORTF(3, 18))
-#define PWM2_GPIO (FUNC(3) | PORTF(3, 18))
-#define PWM1 (FUNC(0) | PORTF(3, 17))
-#define PWM1_I2C1_SDA (FUNC(1) | PORTF(3, 17))
-#define PWM1_DUART_TX (FUNC(2) | PORTF(3, 17))
-#define PWM1_GPIO (FUNC(3) | PORTF(3, 17))
-#define PWM0 (FUNC(0) | PORTF(3, 16))
-#define PWM0_I2C1_SCL (FUNC(1) | PORTF(3, 16))
-#define PWM0_DUART_RX (FUNC(2) | PORTF(3, 16))
-#define PWM0_GPIO (FUNC(3) | PORTF(3, 16))
+#define PWM2 (FUNC(0) | PORTF(3, 18) | SE | VE | PE)
+#define PWM2_USB0_ID (FUNC(1) | PORTF(3, 18) | SE | VE | PE)
+#define PWM2_USB1_OC (FUNC(2) | PORTF(3, 18) | SE | VE | PE)
+#define PWM2_GPIO (FUNC(3) | PORTF(3, 18) | SE | VE | PE)
+#define PWM1 (FUNC(0) | PORTF(3, 17) | SE | VE | BK)
+#define PWM1_I2C1_SDA (FUNC(1) | PORTF(3, 17) | SE | VE | BK)
+#define PWM1_DUART_TX (FUNC(2) | PORTF(3, 17) | SE | VE | BK)
+#define PWM1_GPIO (FUNC(3) | PORTF(3, 17) | SE | VE | BK)
+#define PWM0 (FUNC(0) | PORTF(3, 16) | SE | VE | BK)
+#define PWM0_I2C1_SCL (FUNC(1) | PORTF(3, 16) | SE | VE | BK)
+#define PWM0_DUART_RX (FUNC(2) | PORTF(3, 16) | SE | VE | BK)
+#define PWM0_GPIO (FUNC(3) | PORTF(3, 16) | SE | VE | BK)
#define AUART3_RTS (FUNC(0) | PORTF(3, 15) | SE | VE | BK)
#define AUART3_RTS_CAN1_RX (FUNC(1) | PORTF(3, 15) | SE | VE | BK)
#define AUART3_RTS_ENET0_1588_EVENT1_IN (FUNC(2) | PORTF(3, 15) | SE | VE | BK)
#define AUART3_RTS_GPIO (FUNC(3) | PORTF(3, 15) | SE | VE | BK)
-#define AUART3_CTS (FUNC(0) | PORTF(3, 14) | SE | VE | BK | BK)
+#define AUART3_CTS (FUNC(0) | PORTF(3, 14) | SE | VE | BK)
#define AUART3_CTS_CAN1_TX (FUNC(1) | PORTF(3, 14) | SE | VE | BK)
#define AUART3_CTS_ENET0_1588_EVENT1_OUT (FUNC(2) | PORTF(3, 14) | SE | VE | BK)
#define AUART3_CTS_GPIO (FUNC(3) | PORTF(3, 14) | SE | VE | BK)
--
2.1.1
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