[PATCH V2] sama5d3x: fix AT91_SMC_CS offset stride

[Matteo Fortini]

As stated in section 29.19.32 of SAMA5D3 Series datasheet, to move
from CS(n) to CS(n+1) the stride is 0x14 and not 0x10 as in the
other AT91 CPUs

Signed-off-by: Matteo Fortini <matteo.fortini at gmail.com>
---
 arch/arm/mach-at91/sam9_smc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index a137da4..6dd3797 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -12,11 +12,13 @@
 #include <init.h>
 #include <io.h>
 #include <mach/hardware.h>
+#include <mach/cpu.h>
 #include <mach/io.h>
 
 #include <mach/at91sam9_smc.h>
 
-#define AT91_SMC_CS(id, n)	(smc_base_addr[id] + ((n) * 0x10))
+#define AT91_SMC_CS_STRIDE      ((at91_soc_initdata.type == AT91_SOC_SAMA5D3)?0x14:0x10)
+#define AT91_SMC_CS(id, n)	(smc_base_addr[id] + ((n) * AT91_SMC_CS_STRIDE))
 
 static void __iomem *smc_base_addr[2];
 
-- 
2.0.0.rc2