[PATCH 2/2] ARM: i.MX6: correct work flow of PFDs from uboot-sources

[Sascha Hauer]

From: Jesús Guitarte <jguitarte at data-modul.com>

PFDs need to be gate/ungate after PLL lock to reset PFDs to right state.
Otherwise PFDs may lose correct state in state-machine, then no output
clock.
For i.MX6DL and i.MX6SL, ROM have taken care of PFD396 already since the
bus clock needs it.

This patch is backported from
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/cpu/arm_cortexa8/mx6/generic.c?h=imx_v2009.08_3.0.35_4.1.0&id=b7c5badf94ffbe6cd0845efbb75e16e05e3af404

And resolve issues with booting from MMC/SD cards

Signed-off-by: Jesús Guitarte <jguitarte at data-modul.com>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 13d8bfa..304b1c0 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -18,6 +18,7 @@
 #include <mach/imx6.h>
 #include <mach/generic.h>
 #include <mach/revision.h>
+#include <mach/imx6-anadig.h>
 #include <mach/imx6-regs.h>
 #include <mach/generic.h>
 
@@ -27,6 +28,7 @@ void imx6_init_lowlevel(void)
 {
 	void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
 	void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
+	int is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
 
 	/*
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -56,6 +58,35 @@ void imx6_init_lowlevel(void)
 	writel(0xffffffff, 0x020c4078);
 	writel(0xffffffff, 0x020c407c);
 	writel(0xffffffff, 0x020c4080);
+
+	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
+	 * to make sure PFD is working right, otherwise, PFDs may
+	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
+	 * workaround in ROM code, as bus clock need it
+	 */
+	writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
+			BM_ANADIG_PFD_480_PFD2_CLKGATE |
+			BM_ANADIG_PFD_480_PFD1_CLKGATE |
+			BM_ANADIG_PFD_480_PFD0_CLKGATE,
+			MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
+	writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
+			(is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+			BM_ANADIG_PFD_528_PFD1_CLKGATE |
+			BM_ANADIG_PFD_528_PFD0_CLKGATE,
+			MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
+
+	writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
+			BM_ANADIG_PFD_480_PFD2_CLKGATE |
+			BM_ANADIG_PFD_480_PFD1_CLKGATE |
+			BM_ANADIG_PFD_480_PFD0_CLKGATE,
+			MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
+	writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
+			(is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+			BM_ANADIG_PFD_528_PFD2_CLKGATE |
+			BM_ANADIG_PFD_528_PFD1_CLKGATE |
+			BM_ANADIG_PFD_528_PFD0_CLKGATE,
+			MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
+
 }
 
 int imx6_init(void)
-- 
1.8.5.2