[PATCH 2/2] ARM i.MX31 pcm037: fix erroneous IOMUX GPR setup in pcm037_usb_init()

[Andreas Pretzsch]

In commit ad09b59f8bb58c27e3872b41f41beb1b9eb1aeb1 "ARM i.MX31: give
register base addresses a proper MX31_ prefix", the IOMUX GPR setup
to enable USBH2 was replaced with an incorrect source register.
Instead of reading the GPR register, USBOTG HWHOST is used as rmw source,
which contains 0x10020001.
Beside the intended GPR[11] setup ("Enable USBH2 signals on AudioPort 3 and
AudioPort6"), this erroneously also sets
	GPR[28] enable USBOTG loopback
	GPR[17] override DSR_DCE1 with USBOTG_DATA4
	GPR[0]  select FIR DMA requests instead of UART2 DMA

Beside breaking UART2, it probably also broke some UART1 and USB OTG setups.
Fix this and replace the address with the appropriate defines.

Signed-off-by: Andreas Pretzsch <apr at cn-eng.de>
---
 arch/arm/boards/pcm037/pcm037.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index 276f9cd..9361a9d 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -83,9 +83,9 @@ static void pcm037_usb_init(void)
 	ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x170), 1);
 
 	/* Host 2 */
-	tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x8);
-	tmp |= 1 << 11;
-	writel(tmp, MX31_IOMUXC_BASE_ADDR + 0x8);
+	tmp = readl(MX31_IOMUXC_GPR);
+	tmp |= 1 << 11;	/* IOMUX GPR: enable USBH2 signals */
+	writel(tmp, MX31_IOMUXC_GPR);
 
 	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC));
 	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC));
-- 
1.7.10.4