[PATCH v2 0/8] DDR2 memory initialisaion

[Sascha Hauer]

Hi Renaud,

On Tue, Jun 25, 2013 at 11:45:29AM +0100, Renaud Barbier wrote:
> This patch set adds memory initialisation through SPD data for
> Freescale CPUs such as the mpc8544. It is based on U-Boot tree id
> a71d45d706a5b51c34
> 
> Support for DDR1, DDR3 and memory interleaving has been removed as
> the code is aimed at the GEIP DA923RC board. Support for this
> board will be submitted after approval of these patches by the
> barebox community.
> 
> In addition, early I2C read access has been added so that the SPD
> data can be retrieved from the I2C eeprom.

This code won't win beauty prices. However, since my main concern
of having lots of board specific defines in common code are resolved
and this code only touches architecture stuff I should be fine with
it.

There's still a lot of room for improvements. I could probably review
this code to death, but I think we both have better things to do ;)

So let's go for it with the little comment fixed I made inline.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |