[PATCH 04/17] ARM: MXS: Add MXS specific clk types

[Jürgen Beisert]

With the following patch on top of [PATCH 04/17]:

diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c
index d62ebfc..7ff5527 100644
--- a/drivers/clk/mxs/clk-ref.c
+++ b/drivers/clk/mxs/clk-ref.c
@@ -40,6 +40,17 @@ struct clk_ref {
 #define SET	0x4
 #define CLR	0x8
 
+static int clk_ref_is_enabled(struct clk *clk)
+{
+	struct clk_ref *ref = to_clk_ref(clk);
+	u32 reg = readl(ref->reg);
+
+	if (reg & 1 << ((ref->idx + 1) * 8 - 1))
+		return 0;
+
+	return 1;
+}
+
 static int clk_ref_enable(struct clk *clk)
 {
 	struct clk_ref *ref = to_clk_ref(clk);
@@ -118,6 +129,7 @@ static int clk_ref_set_rate(struct clk *clk, unsigned long rate,
 }
 
 static const struct clk_ops clk_ref_ops = {
+	.is_enabled	= clk_ref_is_enabled,
 	.enable		= clk_ref_enable,
 	.disable	= clk_ref_disable,
 	.recalc_rate	= clk_ref_recalc_rate,

...I get the expected output at runtime (e.g. CPU and EMI clocks get
reported as 'enabled'):

luma:/ clk_dump
ref_xtal (rate 24000000, enabled)
    pll (rate 480000000, enabled)
        ref_cpu (rate 454736842, enabled) <---------
            cpu_pll (rate 454736842, enabled)
                cpu (rate 454736842, enabled)
                    hbus (rate 151578947, enabled)
        ref_emi (rate 261818181, enabled) <---------
            emi_pll (rate 130909090, enabled)
                emi_sel (rate 130909090, enabled)
                    emi (rate 130909090, enabled)
        ref_pix (rate 480000000, disabled)
            lcdif_sel (rate 480000000, disabled)
                lcdif_div (rate 480000000, disabled)
                    lcdif (rate 480000000, disabled)
        ref_io (rate 480000000, enabled)
            ssp_sel (rate 480000000, enabled)
                ssp_div (rate 96000000, enabled)
                    ssp (rate 96000000, enabled)
        spdif_div (rate 120000000, enabled)
            spdif (rate 120000000, disabled)
    saif_sel (rate 24000000, enabled)
        saif_div (rate 366, enabled)
            saif (rate 366, disabled)
    gpmi_sel (rate 24000000, enabled)
        gpmi_div (rate 24000000, enabled)
            gpmi (rate 24000000, disabled)
    etm_sel (rate 24000000, enabled)
        etm_div (rate 24000000, enabled)
            etm (rate 24000000, disabled)
    cpu_xtal (rate 24000000, enabled)
    xbus (rate 24000000, enabled)
    emi_xtal (rate 24000000, enabled)
    clk32k_div (rate 32000, enabled)
        clk32k (rate 32000, enabled)
            adc (rate 2000, enabled)
    rtc (rate 31250, enabled)
    dri (rate 24000000, disabled)
    pwm (rate 24000000, disabled)
    filt (rate 24000000, disabled)
    uart (rate 24000000, enabled)

jbe

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