[PATCH v2 3/9] ARM: clps711x: Adds config option for CPU PLL multiplier

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:41 Wed 13 Feb     , Alexander Shiyan wrote:
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> ---
>  arch/arm/boards/clep7212/lowlevel.c            |    6 +++++-
>  arch/arm/mach-clps711x/Kconfig                 |   13 +++++++++++++
>  arch/arm/mach-clps711x/include/mach/clps711x.h |    2 +-
>  arch/arm/mach-clps711x/lowlevel.c              |    7 +++++--
>  4 files changed, 24 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> index b7d6d1d..fcf8285 100644
> --- a/arch/arm/boards/clep7212/lowlevel.c
> +++ b/arch/arm/boards/clep7212/lowlevel.c
> @@ -14,9 +14,13 @@
>  
>  #include <mach/clps711x.h>
>  
> +#if (CONFIG_CLPS711X_CPU_PLL_MULT < 20) || (CONFIG_CLPS711X_CPU_PLL_MULT > 50)
> +# error "CPU PLL multiplier out of range"
> +#endif
> +
>  void __naked __bare_init barebox_arm_reset_vector(void)
>  {
>  	arm_cpu_lowlevel_init();
>  
> -	clps711x_barebox_entry();
> +	clps711x_barebox_entry(CONFIG_CLPS711X_CPU_PLL_MULT);
>  }
> diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
> index f0adeda..d2873b4 100644
> --- a/arch/arm/mach-clps711x/Kconfig
> +++ b/arch/arm/mach-clps711x/Kconfig
> @@ -10,6 +10,19 @@ config MACH_CLEP7212
>  
>  endchoice
>  
> +menu "CLPS711X specific settings"
> +
> +config CLPS711X_CPU_PLL_MULT
> +	int "CPU PLL multiplier (20-50)"
> +	range 20 50
> +	default "40"
> +	help
> +	  Define CPU PLL multiplier. PLL is calculated by formula:
> +	    PLL Frequency = (PLL Multiplier / 2) * 3686400 Hz
> +	  Default value is 40, for achieve 73 MHz.
> +
Nack NO KConfig for such sensitve value

if it's soc detect it I do not have the datasheet but I'm sure you can

Best Regards,
J.
> +endmenu
> +
>  config BOARDINFO
>  	default "Cirrus Logic CLEP7212" if MACH_CLEP7212
>  
> diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
> index 5b8fe82..cc65cc8 100644
> --- a/arch/arm/mach-clps711x/include/mach/clps711x.h
> +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
> @@ -281,6 +281,6 @@
>  #define MEMCFG_WAITSTATE_2_0	(14 << 2)
>  #define MEMCFG_WAITSTATE_1_0	(15 << 2)
>  
> -void clps711x_barebox_entry(void);
> +void clps711x_barebox_entry(u32);
>  
>  #endif
> diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
> index cd3216a..193f61a 100644
> --- a/arch/arm/mach-clps711x/lowlevel.c
> +++ b/arch/arm/mach-clps711x/lowlevel.c
> @@ -17,9 +17,8 @@
>  
>  #include <mach/clps711x.h>
>  
> -void __naked __bare_init clps711x_barebox_entry(void)
> +void __naked __bare_init clps711x_barebox_entry(u32 pllmult)
>  {
> -	const u32 pllmult = 50;
>  	u32 cpu, bus;
>  
>  	/* Setup base clocking, Enable SDQM pins  */
> @@ -28,6 +27,10 @@ void __naked __bare_init clps711x_barebox_entry(void)
>  
>  	/* Check if we running from external 13 MHz clock */
>  	if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) {
> +		/* Check valid multiplier, default to 74 MHz */
> +		if ((pllmult < 20) || (pllmult > 50))
> +			pllmult = 40;
> +
>  		/* Setup PLL */
>  		writel(pllmult << 24, PLLW);
>  		asm("nop");
> -- 
> 1.7.3.4
> 
> 
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