[PATCH] mtd: nand: extend NAND flash detection to new MLC chips

[Sascha Hauer]

Hi Marcus,

On Sat, Sep 15, 2012 at 01:45:06PM +0200, Marcus Folkesson wrote:
> Some of the newer MLC devices have a 6-byte ID sequence in which
> several field definitions differ from older chips in a manner that is
> not backward compatible.
> 
> This method is already used in the Linux Kernel.
> 
> Signed-off-by: Marcus Folkesson <marcus.folkesson at gmail.com>

Applied, thanks. I dropped the patch adding one of the new nand ids
below from next in favour for this more complete list of new nand ids.

> diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
> index cb53fc6..73d4cc2 100644
> --- a/drivers/mtd/nand/nand_ids.c
> +++ b/drivers/mtd/nand/nand_ids.c
> @@ -107,17 +107,47 @@ struct nand_flash_dev nand_flash_ids[] = {
>  	{__NANDSTR("NAND 512MiB 3,3V 16-bit"),	0xCC, 0, 512, 0, LP_OPTIONS16},
>  
>  	/* 8 Gigabit */
> -	{__NANDSTR("NAND 1GiB 1,8V 8-bit"),	0xA3, 0, 1024, 0, LP_OPTIONS},
> -	{__NANDSTR("NAND 1GiB 3,3V 8-bit"),	0xD3, 0, 1024, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 1GiB 1,8V 8-bit"),		0xA3, 0, 1024, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 1GiB 3,3V 8-bit"),		0xD3, 0, 1024, 0, LP_OPTIONS},
>  	{__NANDSTR("NAND 1GiB 1,8V 16-bit"),	0xB3, 0, 1024, 0, LP_OPTIONS16},
>  	{__NANDSTR("NAND 1GiB 3,3V 16-bit"),	0xC3, 0, 1024, 0, LP_OPTIONS16},
>  
>  	/* 16 Gigabit */
> -	{__NANDSTR("NAND 2GiB 1,8V 8-bit"),	0xA5, 0, 2048, 0, LP_OPTIONS},
> -	{__NANDSTR("NAND 2GiB 3,3V 8-bit"),	0xD5, 0, 2048, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 2GiB 1,8V 8-bit"),		0xA5, 0, 2048, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 2GiB 3,3V 8-bit"),		0xD5, 0, 2048, 0, LP_OPTIONS},
>  	{__NANDSTR("NAND 2GiB 1,8V 16-bit"),	0xB5, 0, 2048, 0, LP_OPTIONS16},
>  	{__NANDSTR("NAND 2GiB 3,3V 16-bit"),	0xC5, 0, 2048, 0, LP_OPTIONS16},
>  
> +	/* 32 Gigabit */
> +	{__NANDSTR("NAND 4GiB 1,8V 8-bit"),		0xA7, 0, 4096, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 4GiB 3,3V 8-bit"),		0xD7, 0, 4096, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 4GiB 1,8V 16-bit"),	0xB7, 0, 4096, 0, LP_OPTIONS16},
> +	{__NANDSTR("NAND 4GiB 3,3V 16-bit"),	0xC7, 0, 4096, 0, LP_OPTIONS16},
> +
> +	/* 64 Gigabit */
> +	{__NANDSTR("NAND 8GiB 1,8V 8-bit"),		0xAE, 0, 8192, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 8GiB 3,3V 8-bit"),		0xDE, 0, 8192, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 8GiB 1,8V 16-bit"),	0xBE, 0, 8192, 0, LP_OPTIONS16},
> +	{__NANDSTR("NAND 8GiB 3,3V 16-bit"),	0xCE, 0, 8192, 0, LP_OPTIONS16},
> +
> +	/* 128 Gigabit */
> +	{__NANDSTR("NAND 16GiB 1,8V 8-bit"),	0x1A, 0, 16384, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 16GiB 3,3V 8-bit"),	0x3A, 0, 16384, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 16GiB 1,8V 16-bit"),	0x2A, 0, 16384, 0, LP_OPTIONS16},
> +	{__NANDSTR("NAND 16GiB 3,3V 16-bit"),	0x4A, 0, 16384, 0, LP_OPTIONS16},
> +
> +	/* 256 Gigabit */
> +	{__NANDSTR("NAND 32GiB 1,8V 8-bit"),	0x1C, 0, 32768, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 32GiB 3,3V 8-bit"),	0x3C, 0, 32768, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 32GiB 1,8V 16-bit"),	0x2C, 0, 32768, 0, LP_OPTIONS16},
> +	{__NANDSTR("NAND 32GiB 3,3V 16-bit"),	0x4C, 0, 32768, 0, LP_OPTIONS16},
> +
> +	/* 512 Gigabit */
> +	{__NANDSTR("NAND 64GiB 1,8V 8-bit"),	0x1E, 0, 65536, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 64GiB 3,3V 8-bit"),	0x3E, 0, 65536, 0, LP_OPTIONS},
> +	{__NANDSTR("NAND 64GiB 1,8V 16-bit"),	0x2E, 0, 65536, 0, LP_OPTIONS16},
> +	{__NANDSTR("NAND 64GiB 3,3V 16-bit"),	0x4E, 0, 65536, 0, LP_OPTIONS16},

BTW do you have one of those chips > 4GiB? I bet barebox does not work out
of the box with these.

Sascha


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