[RFC 0/3] MIPS: import CPU and cache detection code from Linux
antonynpavlov at gmail.com
Mon May 21 04:07:08 EDT 2012
THE PATCHES HAVE PRELIMINARY STATUS. PLEASE, DON'T COMMIT IT!
The patches lack support of Ingenic and Broadcom chips!
This patch series introduces MIPS cache support to barebox.
It adds functions to detect CPU capabilities.
[RFC 1/3] MIPS: introduce C architecture-specific low-level init
[RFC 2/3] MIPS: import CPU and cache detection code from Linux
[RFC 3/3] MIPS: cpuinfo: import CPU message from Linux
More information about the barebox