[PATCH 2/4] Fine split S3C arch dependencies from generic code

Alexey Galakhov agalakhov at gmail.com
Fri May 4 06:52:52 EDT 2012

On 04.05.2012 15:58, Juergen Beisert wrote:
> No it hasn't. Believe me. Using the old 1 bit ECC (and also the 4 bit ECC) 
> makes no sense any more. Even the built-in iROM forces the 8 bit ECC mode if 
> you want to boot it from NAND. And I guess it is the same on the S5P CPU.

Ok, how about using nand-s3c.c for generic read and write procedures
(same for all S3C and S5P) and adding nand-s3c-mlc.c for MLC ECC support

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