[PATCH 2/4] dma: add mxs-apbh-dma driver
Sascha Hauer
s.hauer at pengutronix.de
Thu Jun 7 17:04:56 EDT 2012
From: Wolfram Sang <w.sang at pengutronix.de>
Based on the U-Boot version. Changed to kernel style register layout, added
MX23 support, made MMU aware and adapted to barebox.
Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
arch/arm/mach-mxs/include/mach/dma.h | 145 +++++++++
drivers/Kconfig | 1 +
drivers/Makefile | 1 +
drivers/dma/Kconfig | 8 +
drivers/dma/Makefile | 1 +
drivers/dma/apbh_dma.c | 598 ++++++++++++++++++++++++++++++++++
6 files changed, 754 insertions(+)
create mode 100644 arch/arm/mach-mxs/include/mach/dma.h
create mode 100644 drivers/dma/Kconfig
create mode 100644 drivers/dma/Makefile
create mode 100644 drivers/dma/apbh_dma.c
diff --git a/arch/arm/mach-mxs/include/mach/dma.h b/arch/arm/mach-mxs/include/mach/dma.h
new file mode 100644
index 0000000..52747e2
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/dma.h
@@ -0,0 +1,145 @@
+/*
+ * Freescale i.MX28 APBH DMA
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut at gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __DMA_H__
+#define __DMA_H__
+
+#include <linux/list.h>
+
+#ifndef CONFIG_ARCH_DMA_PIO_WORDS
+#define DMA_PIO_WORDS 15
+#else
+#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
+#endif
+
+#define MXS_DMA_ALIGNMENT 32
+
+/*
+ * MXS DMA channels
+ */
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP2,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP,
+ MXS_MAX_DMA_CHANNELS,
+};
+
+/*
+ * MXS DMA hardware command.
+ *
+ * This structure describes the in-memory layout of an entire DMA command,
+ * including space for the maximum number of PIO accesses. See the appropriate
+ * reference manual for a detailed description of what these fields mean to the
+ * DMA hardware.
+ */
+#define MXS_DMA_DESC_COMMAND_MASK 0x3
+#define MXS_DMA_DESC_COMMAND_OFFSET 0
+#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
+#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
+#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
+#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
+#define MXS_DMA_DESC_CHAIN (1 << 2)
+#define MXS_DMA_DESC_IRQ (1 << 3)
+#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
+#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
+#define MXS_DMA_DESC_DEC_SEM (1 << 6)
+#define MXS_DMA_DESC_WAIT4END (1 << 7)
+#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
+#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
+#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
+#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
+#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
+#define MXS_DMA_DESC_BYTES_OFFSET 16
+
+struct mxs_dma_cmd {
+ unsigned long next;
+ unsigned long data;
+ union {
+ dma_addr_t address;
+ unsigned long alternate;
+ };
+ unsigned long pio_words[DMA_PIO_WORDS];
+};
+
+/*
+ * MXS DMA command descriptor.
+ *
+ * This structure incorporates an MXS DMA hardware command structure, along
+ * with metadata.
+ */
+#define MXS_DMA_DESC_FIRST (1 << 0)
+#define MXS_DMA_DESC_LAST (1 << 1)
+#define MXS_DMA_DESC_READY (1 << 31)
+
+struct mxs_dma_desc {
+ struct mxs_dma_cmd cmd;
+ unsigned int flags;
+ dma_addr_t address;
+ void *buffer;
+ struct list_head node;
+};
+
+/**
+ * MXS DMA channel
+ *
+ * This structure represents a single DMA channel. The MXS platform code
+ * maintains an array of these structures to represent every DMA channel in the
+ * system (see mxs_dma_channels).
+ */
+#define MXS_DMA_FLAGS_IDLE 0
+#define MXS_DMA_FLAGS_BUSY (1 << 0)
+#define MXS_DMA_FLAGS_FREE 0
+#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
+#define MXS_DMA_FLAGS_VALID (1 << 31)
+
+struct mxs_dma_chan {
+ const char *name;
+ unsigned long dev;
+ struct mxs_dma_device *dma;
+ unsigned int flags;
+ unsigned int active_num;
+ unsigned int pending_num;
+ struct list_head active;
+ struct list_head done;
+};
+
+struct mxs_dma_desc *mxs_dma_desc_alloc(void);
+void mxs_dma_desc_free(struct mxs_dma_desc *);
+int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
+
+int mxs_dma_go(int chan);
+int mxs_dma_init(void);
+
+#endif /* __DMA_H__ */
diff --git a/drivers/Kconfig b/drivers/Kconfig
index c52c56a..037b0d4 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -17,5 +17,6 @@ source "drivers/eeprom/Kconfig"
source "drivers/input/Kconfig"
source "drivers/pwm/Kconfig"
+source "drivers/dma/Kconfig"
endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 3aefc12..f40b321 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_LED) += led/
obj-y += eeprom/
obj-$(CONFIG_PWM) += pwm/
obj-y += input/
+obj-y += dma/
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
new file mode 100644
index 0000000..ec6c894
--- /dev/null
+++ b/drivers/dma/Kconfig
@@ -0,0 +1,8 @@
+menu "DMA support"
+
+config MXS_APBH_DMA
+ tristate "MXS APBH DMA ENGINE"
+ depends on ARCH_IMX23 || ARCH_IMX28
+ help
+ Experimental!
+endmenu
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
new file mode 100644
index 0000000..7a3a3b2
--- /dev/null
+++ b/drivers/dma/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MXS_APBH_DMA) += apbh_dma.o
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
new file mode 100644
index 0000000..363878f
--- /dev/null
+++ b/drivers/dma/apbh_dma.c
@@ -0,0 +1,598 @@
+/*
+ * Freescale i.MX28 APBH DMA driver
+ *
+ * Copyright (C) 2011 Wolfram Sang <w.sang at pengutronix.de>
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut at gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/list.h>
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <mach/clock.h>
+#include <mach/imx-regs.h>
+#include <mach/dma.h>
+#include <mach/mxs.h>
+
+#define HW_APBHX_CTRL0 0x000
+#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
+#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
+#define BP_APBH_CTRL0_CLKGATE_CHANNEL 8
+#define BP_APBH_CTRL0_RESET_CHANNEL 16
+#define HW_APBHX_CTRL1 0x010
+#define BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN 16
+#define HW_APBHX_CTRL2 0x020
+#define HW_APBHX_CHANNEL_CTRL 0x030
+#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
+#define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800)
+#define HW_APBX_VERSION 0x800
+#define BP_APBHX_VERSION_MAJOR 24
+#define HW_APBHX_CHn_NXTCMDAR(n) \
+ ((apbh_is_old ? 0x050 : 0x110) + (n) * 0x70)
+#define HW_APBHX_CHn_SEMA(n) \
+ ((apbh_is_old ? 0x080 : 0x140) + (n) * 0x70)
+#define BM_APBHX_CHn_SEMA_PHORE (0xff << 16)
+#define BP_APBHX_CHn_SEMA_PHORE 16
+
+static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
+static bool apbh_is_old;
+
+/*
+ * Test is the DMA channel is valid channel
+ */
+int mxs_dma_validate_chan(int channel)
+{
+ struct mxs_dma_chan *pchan;
+
+ if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
+ return -EINVAL;
+
+ pchan = mxs_dma_channels + channel;
+ if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+ return -EINVAL;
+
+ return 0;
+}
+
+/*
+ * Return the address of the command within a descriptor.
+ */
+static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
+{
+ return desc->address + offsetof(struct mxs_dma_desc, cmd);
+}
+
+/*
+ * Read a DMA channel's hardware semaphore.
+ *
+ * As used by the MXS platform's DMA software, the DMA channel's hardware
+ * semaphore reflects the number of DMA commands the hardware will process, but
+ * has not yet finished. This is a volatile value read directly from hardware,
+ * so it must be be viewed as immediately stale.
+ *
+ * If the channel is not marked busy, or has finished processing all its
+ * commands, this value should be zero.
+ *
+ * See mxs_dma_append() for details on how DMA command blocks must be configured
+ * to maintain the expected behavior of the semaphore's value.
+ */
+static int mxs_dma_read_semaphore(int channel)
+{
+ void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+ uint32_t tmp;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ tmp = readl(apbh_regs + HW_APBHX_CHn_SEMA(channel));
+
+ tmp &= BM_APBHX_CHn_SEMA_PHORE;
+ tmp >>= BP_APBHX_CHn_SEMA_PHORE;
+
+ return tmp;
+}
+
+/*
+ * Enable a DMA channel.
+ *
+ * If the given channel has any DMA descriptors on its active list, this
+ * function causes the DMA hardware to begin processing them.
+ *
+ * This function marks the DMA channel as "busy," whether or not there are any
+ * descriptors to process.
+ */
+static int mxs_dma_enable(int channel)
+{
+ void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+ unsigned int sem;
+ struct mxs_dma_chan *pchan;
+ struct mxs_dma_desc *pdesc;
+ int channel_bit, ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ pchan = mxs_dma_channels + channel;
+
+ if (pchan->pending_num == 0) {
+ pchan->flags |= MXS_DMA_FLAGS_BUSY;
+ return 0;
+ }
+
+ pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
+ if (pdesc == NULL)
+ return -EFAULT;
+
+ if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
+ if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
+ return 0;
+
+ sem = mxs_dma_read_semaphore(channel);
+ if (sem == 0)
+ return 0;
+
+ if (sem == 1) {
+ pdesc = list_entry(pdesc->node.next,
+ struct mxs_dma_desc, node);
+ writel(mxs_dma_cmd_address(pdesc),
+ apbh_regs + HW_APBHX_CHn_NXTCMDAR(channel));
+ }
+ writel(pchan->pending_num,
+ apbh_regs + HW_APBHX_CHn_SEMA(channel));
+ pchan->active_num += pchan->pending_num;
+ pchan->pending_num = 0;
+ } else {
+ pchan->active_num += pchan->pending_num;
+ pchan->pending_num = 0;
+ writel(mxs_dma_cmd_address(pdesc),
+ apbh_regs + HW_APBHX_CHn_NXTCMDAR(channel));
+ writel(pchan->active_num,
+ apbh_regs + HW_APBHX_CHn_SEMA(channel));
+ channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
+ writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + BIT_CLR);
+ }
+
+ pchan->flags |= MXS_DMA_FLAGS_BUSY;
+ return 0;
+}
+
+/*
+ * Disable a DMA channel.
+ *
+ * This function shuts down a DMA channel and marks it as "not busy." Any
+ * descriptors on the active list are immediately moved to the head of the
+ * "done" list, whether or not they have actually been processed by the
+ * hardware. The "ready" flags of these descriptors are NOT cleared, so they
+ * still appear to be active.
+ *
+ * This function immediately shuts down a DMA channel's hardware, aborting any
+ * I/O that may be in progress, potentially leaving I/O hardware in an undefined
+ * state. It is unwise to call this function if there is ANY chance the hardware
+ * is still processing a command.
+ */
+static int mxs_dma_disable(int channel)
+{
+ struct mxs_dma_chan *pchan;
+ void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+ int channel_bit, ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ pchan = mxs_dma_channels + channel;
+
+ if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
+ return -EINVAL;
+
+ channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
+ writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
+
+ pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
+ pchan->active_num = 0;
+ pchan->pending_num = 0;
+ list_splice_init(&pchan->active, &pchan->done);
+
+ return 0;
+}
+
+/*
+ * Resets the DMA channel hardware.
+ */
+static int mxs_dma_reset(int channel)
+{
+ void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ if (apbh_is_old)
+ writel(1 << (channel + BP_APBH_CTRL0_RESET_CHANNEL),
+ apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
+ else
+ writel(1 << (channel + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
+ apbh_regs + HW_APBHX_CHANNEL_CTRL + BIT_SET);
+
+ return 0;
+}
+
+/*
+ * Enable or disable DMA interrupt.
+ *
+ * This function enables the given DMA channel to interrupt the CPU.
+ */
+static int mxs_dma_enable_irq(int channel, int enable)
+{
+ void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ if (enable)
+ writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
+ apbh_regs + HW_APBHX_CTRL1 + BIT_SET);
+ else
+ writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
+ apbh_regs + HW_APBHX_CTRL1 + BIT_CLR);
+
+ return 0;
+}
+
+/*
+ * Clear DMA interrupt.
+ *
+ * The software that is using the DMA channel must register to receive its
+ * interrupts and, when they arrive, must call this function to clear them.
+ */
+static int mxs_dma_ack_irq(int channel)
+{
+ void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ writel(1 << channel, apbh_regs + HW_APBHX_CTRL1 + BIT_CLR);
+ writel(1 << channel, apbh_regs + HW_APBHX_CTRL2 + BIT_CLR);
+
+ return 0;
+}
+
+/*
+ * Request to reserve a DMA channel
+ */
+static int mxs_dma_request(int channel)
+{
+ struct mxs_dma_chan *pchan;
+
+ if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
+ return -EINVAL;
+
+ pchan = mxs_dma_channels + channel;
+ if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
+ return -ENODEV;
+
+ if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
+ return -EBUSY;
+
+ pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
+ pchan->active_num = 0;
+ pchan->pending_num = 0;
+
+ INIT_LIST_HEAD(&pchan->active);
+ INIT_LIST_HEAD(&pchan->done);
+
+ return 0;
+}
+
+/*
+ * Release a DMA channel.
+ *
+ * This function releases a DMA channel from its current owner.
+ *
+ * The channel will NOT be released if it's marked "busy" (see
+ * mxs_dma_enable()).
+ */
+static int mxs_dma_release(int channel)
+{
+ struct mxs_dma_chan *pchan;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ pchan = mxs_dma_channels + channel;
+
+ if (pchan->flags & MXS_DMA_FLAGS_BUSY)
+ return -EBUSY;
+
+ pchan->dev = 0;
+ pchan->active_num = 0;
+ pchan->pending_num = 0;
+ pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
+
+ return 0;
+}
+
+/*
+ * Allocate DMA descriptor
+ */
+struct mxs_dma_desc *mxs_dma_desc_alloc(void)
+{
+ struct mxs_dma_desc *pdesc;
+
+ pdesc = dma_alloc_coherent(sizeof(struct mxs_dma_desc));
+
+ if (pdesc == NULL)
+ return NULL;
+
+ memset(pdesc, 0, sizeof(*pdesc));
+ pdesc->address = (dma_addr_t)pdesc;
+
+ return pdesc;
+};
+
+/*
+ * Free DMA descriptor
+ */
+void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
+{
+ if (pdesc == NULL)
+ return;
+
+ free(pdesc);
+}
+
+/*
+ * Add a DMA descriptor to a channel.
+ *
+ * If the descriptor list for this channel is not empty, this function sets the
+ * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so
+ * it will chain to the new descriptor's command.
+ *
+ * Then, this function marks the new descriptor as "ready," adds it to the end
+ * of the active descriptor list, and increments the count of pending
+ * descriptors.
+ *
+ * The MXS platform DMA software imposes some rules on DMA commands to maintain
+ * important invariants. These rules are NOT checked, but they must be carefully
+ * applied by software that uses MXS DMA channels.
+ *
+ * Invariant:
+ * The DMA channel's hardware semaphore must reflect the number of DMA
+ * commands the hardware will process, but has not yet finished.
+ *
+ * Explanation:
+ * A DMA channel begins processing commands when its hardware semaphore is
+ * written with a value greater than zero, and it stops processing commands
+ * when the semaphore returns to zero.
+ *
+ * When a channel finishes a DMA command, it will decrement its semaphore if
+ * the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
+ *
+ * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set,
+ * unless it suits the purposes of the software. For example, one could
+ * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
+ * bit set only in the last one. Then, setting the DMA channel's hardware
+ * semaphore to one would cause the entire series of five commands to be
+ * processed. However, this example would violate the invariant given above.
+ *
+ * Rule:
+ * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA
+ * channel's hardware semaphore will be decremented EVERY time a command is
+ * processed.
+ */
+int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
+{
+ struct mxs_dma_chan *pchan;
+ struct mxs_dma_desc *last;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ pchan = mxs_dma_channels + channel;
+
+ pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
+ pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
+
+ if (!list_empty(&pchan->active)) {
+ last = list_entry(pchan->active.prev, struct mxs_dma_desc,
+ node);
+
+ pdesc->flags &= ~MXS_DMA_DESC_FIRST;
+ last->flags &= ~MXS_DMA_DESC_LAST;
+
+ last->cmd.next = mxs_dma_cmd_address(pdesc);
+ last->cmd.data |= MXS_DMA_DESC_CHAIN;
+ }
+ pdesc->flags |= MXS_DMA_DESC_READY;
+ if (pdesc->flags & MXS_DMA_DESC_FIRST)
+ pchan->pending_num++;
+ list_add_tail(&pdesc->node, &pchan->active);
+
+ return ret;
+}
+
+/*
+ * Clean up processed DMA descriptors.
+ *
+ * This function removes processed DMA descriptors from the "active" list. Pass
+ * in a non-NULL list head to get the descriptors moved to your list. Pass NULL
+ * to get the descriptors moved to the channel's "done" list. Descriptors on
+ * the "done" list can be retrieved with mxs_dma_get_finished().
+ *
+ * This function marks the DMA channel as "not busy" if no unprocessed
+ * descriptors remain on the "active" list.
+ */
+static int mxs_dma_finish(int channel, struct list_head *head)
+{
+ int sem;
+ struct mxs_dma_chan *pchan;
+ struct list_head *p, *q;
+ struct mxs_dma_desc *pdesc;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ pchan = mxs_dma_channels + channel;
+
+ sem = mxs_dma_read_semaphore(channel);
+ if (sem < 0)
+ return sem;
+
+ if (sem == pchan->active_num)
+ return 0;
+
+ list_for_each_safe(p, q, &pchan->active) {
+ if ((pchan->active_num) <= sem)
+ break;
+
+ pdesc = list_entry(p, struct mxs_dma_desc, node);
+ pdesc->flags &= ~MXS_DMA_DESC_READY;
+
+ if (head)
+ list_move_tail(p, head);
+ else
+ list_move_tail(p, &pchan->done);
+
+ if (pdesc->flags & MXS_DMA_DESC_LAST)
+ pchan->active_num--;
+ }
+
+ if (sem == 0)
+ pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
+
+ return 0;
+}
+
+/*
+ * Wait for DMA channel to complete
+ */
+static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
+{
+ void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+ int ret;
+
+ ret = mxs_dma_validate_chan(chan);
+ if (ret)
+ return ret;
+
+ while (--timeout) {
+ if (readl(apbh_regs + HW_APBHX_CTRL1) & (1 << chan))
+ break;
+ udelay(1);
+ }
+
+ if (timeout == 0) {
+ ret = -ETIMEDOUT;
+ mxs_dma_reset(chan);
+ }
+
+ return ret;
+}
+
+/*
+ * Execute the DMA channel
+ */
+int mxs_dma_go(int chan)
+{
+ uint32_t timeout = 10000;
+ int ret;
+
+ LIST_HEAD(tmp_desc_list);
+
+ mxs_dma_enable_irq(chan, 1);
+ mxs_dma_enable(chan);
+
+ /* Wait for DMA to finish. */
+ ret = mxs_dma_wait_complete(timeout, chan);
+
+ /* Clear out the descriptors we just ran. */
+ mxs_dma_finish(chan, &tmp_desc_list);
+
+ /* Shut the DMA channel down. */
+ mxs_dma_ack_irq(chan);
+ mxs_dma_reset(chan);
+ mxs_dma_enable_irq(chan, 0);
+ mxs_dma_disable(chan);
+
+ return ret;
+}
+
+/*
+ * Initialize the DMA hardware
+ */
+int mxs_dma_init(void)
+{
+ void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+ struct mxs_dma_chan *pchan;
+ int ret, channel;
+ u32 val, reg;
+
+ mxs_reset_block(apbh_regs, 0);
+
+ /* HACK: Get CPUID and determine APBH version */
+ val = readl(0x8001c310) >> 16;
+ if (val == 0x2800)
+ reg = MXS_APBH_BASE + 0x0800;
+ else
+ reg = MXS_APBH_BASE + 0x03f0;
+
+ apbh_is_old = (readl((void *)reg) >> 24) < 3;
+
+ writel(BM_APBH_CTRL0_APB_BURST8_EN,
+ apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
+
+ writel(BM_APBH_CTRL0_APB_BURST_EN,
+ apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
+
+ for (channel = 0; channel < MXS_MAX_DMA_CHANNELS; channel++) {
+ pchan = mxs_dma_channels + channel;
+ pchan->flags = MXS_DMA_FLAGS_VALID;
+
+ ret = mxs_dma_request(channel);
+
+ if (ret) {
+ printf("MXS DMA: Can't acquire DMA channel %i\n",
+ channel);
+
+ goto err;
+ }
+
+ mxs_dma_reset(channel);
+ mxs_dma_ack_irq(channel);
+ }
+
+ return 0;
+
+err:
+ while (--channel >= 0)
+ mxs_dma_release(channel);
+ return ret;
+}
--
1.7.10
More information about the barebox
mailing list