[PATCH] Avoid SDRAM access crash

[Steve Schefter]

Hi Sascha.

> I wonder why this has never hit me. On what hardware did you see this?

Me too.  All I can say is that the timing is tight.  I see crashes at 
various DRAM addresses, all depending on how much was left in cache when 
the tlb invalidate was done.

I'm using the Phytec phyCORE-OMAP44xx card.

> Does the following patch solve your problem aswell?

It does.  I see that routine contains a cache flush as well.

Regards,
	Steve

>
> 8<----------------------------------------------------
>
> ARM mmu: flush page tables in arm_mmu_remap_sdram()
>
> Signed-off-by: Sascha Hauer<s.hauer at pengutronix.de>
> ---
>   arch/arm/cpu/mmu.c |    5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
> index 55b07a4..607f357 100644
> --- a/arch/arm/cpu/mmu.c
> +++ b/arch/arm/cpu/mmu.c
> @@ -147,7 +147,7 @@ static int arm_mmu_remap_sdram(struct memory_bank *bank)
>   	if ((phys&  (SZ_1M - 1)) || (bank->size&  (SZ_1M - 1)))
>   		return -EINVAL;
>
> -	ptes = memalign(0x400, num_ptes * sizeof(u32));
> +	ptes = memalign(PAGE_SIZE, num_ptes * sizeof(u32));
>
>   	debug("ptes: 0x%p ttb_start: 0x%08lx ttb_end: 0x%08lx\n",
>   			ptes, ttb_start, ttb_end);
> @@ -165,6 +165,9 @@ static int arm_mmu_remap_sdram(struct memory_bank *bank)
>   		pte += 256;
>   	}
>
> +	dma_flush_range((unsigned long)ttb, (unsigned long)ttb + 0x4000);
> +	dma_flush_range((unsigned long)ptes, num_ptes * sizeof(u32));
> +
>   	tlb_invalidate();
>
>   	return 0;