[PATCH] ARM: mark 'lr' as clobbered by inline assembler

[Enrico Scholz]

When executing 'bl' in inline assembler, the 'lr' register must be
marked as clobbered too.

Signed-off-by: Enrico Scholz <enrico.scholz at sigma-chemnitz.de>
---
 arch/arm/cpu/cpu.c   |    2 +-
 arch/arm/cpu/mmu.c   |    6 +++---
 arch/arm/cpu/start.c |    2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index d4a3b14..fc98844 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -85,7 +85,7 @@ void arch_shutdown(void)
 		"bl __mmu_cache_off;"
 		:
 		:
-		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
+		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
 	);
 #endif
 }
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 8e4e81a..29e12b7 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -24,7 +24,7 @@ static void create_sections(unsigned long virt, unsigned long phys, int size_m,
 		"bl __mmu_cache_flush;"
 		:
 		:
-		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
+		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
 	);
 }
 
@@ -244,7 +244,7 @@ static int mmu_init(void)
 		"bl __mmu_cache_on;"
 		:
 		:
-		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
+		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
         );
 
 	/*
@@ -274,7 +274,7 @@ void mmu_disable(void)
 		"bl __mmu_cache_off;"
 		:
 		:
-		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
+		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
 	);
 }
 
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index ff68783..61d7e3e 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -78,7 +78,7 @@ void __naked __bare_init reset(void)
 		"bl __mmu_cache_flush;"
 		:
 		:
-		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
+		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
 	);
 
 	/* disable MMU stuff and caches */
-- 
1.7.7.4