[PATCH 1/4] eukrea_cpuimx27 : update timings

[Sascha Hauer]

Hi Eric,

On Fri, Jan 15, 2010 at 11:50:16AM +0100, Eric Benard wrote:
> use optimized DDR, NOR & QuadUART timings

Ok, applied for -next.

Sascha

> 
> Signed-off-by: Eric Benard <eric at eukrea.com>
> ---
>  board/eukrea_cpuimx27/eukrea_cpuimx27.c |   12 ++++++------
>  board/eukrea_cpuimx27/lowlevel_init.S   |    4 ++--
>  2 files changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/board/eukrea_cpuimx27/eukrea_cpuimx27.c b/board/eukrea_cpuimx27/eukrea_cpuimx27.c
> index 6878044..629399f 100644
> --- a/board/eukrea_cpuimx27/eukrea_cpuimx27.c
> +++ b/board/eukrea_cpuimx27/eukrea_cpuimx27.c
> @@ -198,9 +198,9 @@ static int eukrea_cpuimx27_devices_init(void)
>  	eukrea_cpuimx27_mmu_init();
>  
>  	/* configure 16 bit nor flash on cs0 */
> -	CS0U = 0x0000CC03;
> -	CS0L = 0xa0330D01;
> -	CS0A = 0x00220800;
> +	CS0U = 0x00008F03;
> +	CS0L = 0xA0330D01;
> +	CS0A = 0x002208C0;
>  
>  	/* initizalize gpios */
>  	for (i = 0; i < ARRAY_SIZE(mode); i++)
> @@ -244,9 +244,9 @@ static int eukrea_cpuimx27_console_init(void)
>  #endif
>  	/* configure 8 bit UART on cs3 */
>  	FMCR &= ~0x2;
> -	CS3U = 0x0000DCF6;
> -	CS3L = 0x444A4541;
> -	CS3A = 0x44443302;
> +	CS3U = 0x0000D603;
> +	CS3L = 0x0D1D0D01;
> +	CS3A = 0x00D20000;
>  #ifdef CONFIG_DRIVER_SERIAL_NS16550
>  	register_device(&quad_uart_serial_device);
>  #endif
> diff --git a/board/eukrea_cpuimx27/lowlevel_init.S b/board/eukrea_cpuimx27/lowlevel_init.S
> index 4622af8..5295a8a 100644
> --- a/board/eukrea_cpuimx27/lowlevel_init.S
> +++ b/board/eukrea_cpuimx27/lowlevel_init.S
> @@ -8,10 +8,10 @@
>  
>  #if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
>  #define ROWS0	ESDCTL_ROW14
> -#define CFG0	0x00695729
> +#define CFG0	0x0029572D
>  #elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
>  #define ROWS0	ESDCTL_ROW13
> -#define CFG0	0x00395B28
> +#define CFG0	0x00095728
>  #endif
>  
>  #define ESDCTL0_VAL (ESDCTL0_SDE | ROWS0 | ESDCTL0_COL10)
> -- 
> 1.6.3.3
> 
> 

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