[PATCH 10/10] PCA100: initialize pll in assembler code

[Sascha Hauer]

The PLL initialisation does not work properly if run from
SDRAM. Move the initialisation code to lowlevel init which
is run in NFC RAM.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 board/phycard-i.MX27/lowlevel_init.S |   18 ++++++++++++++
 board/phycard-i.MX27/pca100.c        |   43 ----------------------------------
 2 files changed, 18 insertions(+), 43 deletions(-)

diff --git a/board/phycard-i.MX27/lowlevel_init.S b/board/phycard-i.MX27/lowlevel_init.S
index 759ecd7..e99dbcf 100644
--- a/board/phycard-i.MX27/lowlevel_init.S
+++ b/board/phycard-i.MX27/lowlevel_init.S
@@ -6,6 +6,7 @@
 
 #include <config.h>
 #include <mach/imx-regs.h>
+#include <mach/imx-pll.h>
 
 #define writel(val, reg) \
 	ldr		r0,	=reg;	\
@@ -72,7 +73,24 @@ board_init_lowlevel:
 	bhi	1f
 
 	mov	pc,r10
+
 1:
+	writel(IMX_PLL_PD(0) |
+		 IMX_PLL_MFD(51) |
+		 IMX_PLL_MFI(7) |
+		 IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */
+
+	writel(IMX_PLL_PD(1) |
+		 IMX_PLL_MFD(12) |
+		 IMX_PLL_MFI(9) |
+		 IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
+
+	writel(CSCR_MPLL_RESTART | CSCR_SPLL_RESTART | CSCR_ARM_SRC_MPLL |
+	       CSCR_MCU_SEL | CSCR_SP_SEL | CSCR_FPM_EN | CSCR_MPEN |
+	       CSCR_SPEN | CSCR_ARM_DIV(0) | CSCR_AHB_DIV(1) | CSCR_USB_DIV(3) |
+	       CSCR_SD_CNT(3) | CSCR_SSI2_SEL | CSCR_SSI1_SEL | CSCR_H264_SEL |
+	       CSCR_MSHC_SEL, CSCR)
+
 	sdram_init
 
 #ifdef CONFIG_NAND_IMX_BOOT
diff --git a/board/phycard-i.MX27/pca100.c b/board/phycard-i.MX27/pca100.c
index fe9b894..d22b327 100644
--- a/board/phycard-i.MX27/pca100.c
+++ b/board/phycard-i.MX27/pca100.c
@@ -237,46 +237,3 @@ void __bare_init nand_boot(void)
 }
 #endif
 
-static int pll_init(void)
-{
-	int i = 0;
-
-        /* for i.MX27 TO2, Set divider of H264_CLK to zero, NFC to 3. */
-	PCDR0 &= ~0x0000FC00;
-
-        /* Configure PCDR */
-        /* Configure PCDR1 */
-	PCDR1 = 0x09030913;
-
-        /* Configure PCCR0 and PCCR1 */
-	PCCR0 = 0x3108480F;
-	PCCR1 |= 0x0780;
-
-	CSCR |= CSCR_UPDATE_DIS;
-
-	MPCTL0 = IMX_PLL_PD(0) |
-		 IMX_PLL_MFD(51) |
-		 IMX_PLL_MFI(7) |
-		 IMX_PLL_MFN(35); /* 399 MHz */
-
-	SPCTL0 = IMX_PLL_PD(1) |
-		 IMX_PLL_MFD(12) |
-		 IMX_PLL_MFI(9) |
-		 IMX_PLL_MFN(3); /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
-
-	CSCR = CSCR_MPLL_RESTART | CSCR_SPLL_RESTART | CSCR_ARM_SRC_MPLL |
-	       CSCR_MCU_SEL | CSCR_SP_SEL | CSCR_FPM_EN | CSCR_MPEN |
-	       CSCR_SPEN | CSCR_ARM_DIV(0) | CSCR_AHB_DIV(3) | CSCR_USB_DIV(3) |
-	       CSCR_SD_CNT(3) | CSCR_SSI2_SEL | CSCR_SSI1_SEL | CSCR_H264_SEL |
-	       CSCR_MSHC_SEL;
-
-	while (i++ < 1000) {
-		while (CCSR & CCSR_32K_SR);
-		while (!(CCSR & CCSR_32K_SR));
-	}
-
-	return 0;
-}
-
-core_initcall(pll_init);
-
-- 
1.6.5.2