Enabling PLL timeout on BCMA bus

[Kalle Valo]

Rafał Miłecki <zajec5 at gmail.com> writes:

> W dniu 16 lipca 2011 03:14 użytkownik Rafał Miłecki <zajec5 at gmail.com> napisał:
>> My last hope is to find some magic in PCI config space.
>
> After dumping PCI config space ops, I've noticed there are writes to 4
> uniq registers:
> 0x0D ← latency timer (setting to 64)
> 0x40 ← Disabling RETRY_TIMEOUT register (0x41)
> 0x80 ← PCI_BAR0_WIN
> 0xAC ← PCI_BAR0_WIN2
>
> No magic here :( I've no idea what now. I don't see a single
> difference between b43 and wl.

What about timing? Maybe wl is slower in some cases?

-- 
Kalle Valo