PIO mode

[Larry Finger]

Paul,

On 10/19/2010 11:22 AM, Paul Fertser wrote:

I do have all the logs you posted.

> MARK 680.950958 Read dword 0xCE035801 from 0x40, devfn: 0
> MARK 680.950966 Wrote dword 0xCE030001 to 0x40, devfn: 0
> 
> And indeed there's code (in the free part of the wl driver) responsible for
> that. Adding that to ssb right after pci_set_master doesn't help though :|

Byte 0x41 of the configuration space is the RETRY_TIMEOUT register. Clearing it
is supposed to keep PCI Tx retries from interfering with C3 CPU state. Similar
code appears in ath9k, ipw2100 and ipw2200 drivers. I think we have tried that
patch in the past, but perhaps the code should be added just in case it might
affect some CPU/device combinations.

Larry