[PATCH v4 08/11] PCI: qcom: Add support for PCIe pre/post_link_speed_change()
Krishna Chaitanya Chundru
krishna.chundru at oss.qualcomm.com
Fri Jul 11 16:11:53 PDT 2025
On 7/12/2025 2:59 AM, Bjorn Helgaas wrote:
> On Mon, Jun 09, 2025 at 04:21:29PM +0530, Krishna Chaitanya Chundru wrote:
>> QCOM PCIe controllers need to disable ASPM before initiating link
>> re-train. So as part of pre_link_speed_change() disable ASPM and as
>> part of post_link_speed_change() enable ASPM back.
>
> Is this a QCOM defect? Or is there something in the PCIe spec about
This is QCOM issue only.
> needing to disable ASPM during retrain? What about
> pcie_retrain_link()? Does that work on QCOM?
After disabling ASPM will work pcie_retrain_link().
- Krishna Chaitanya.
>
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -276,10 +276,16 @@ struct qcom_pcie {
>> struct dentry *debugfs;
>> bool suspended;
>> bool use_pm_opp;
>> + int aspm_state; /* Store ASPM state used in pre & post link speed change */
>
> Whatever this is, it's definitely not an int. Some kind of unsigned
> thing of specified size, at least.
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