[OpenWrt-Devel] [PATCH v3] ath79: ag71xx: apply interface mode to MII0/1_CTRL on ar71xx/ar913x

[Chuanhong Guo]

We currently don't have any code configuring interface mode in ath79,
meaning that we relies on bootloader to set the correct interface mode.

This patch added code to set interface correctly so that everything works
even if bootloader configures it wrong.(e.g. on WNDR3800 u-boot set
the second GMAC mode to RMII but it should be RGMII.)

Introduced "qca,mac-idx" for the difference in MII_CTRL register value.

Signed-off-by: Chuanhong Guo <gch981213 at gmail.com>
---

v2-v3: Changed dt binding

 target/linux/ath79/dts/ar7100.dtsi            |  2 +
 target/linux/ath79/dts/ar9132.dtsi            |  1 +
 .../net/ethernet/atheros/ag71xx/ag71xx_main.c | 64 ++++++++++++++++++-
 3 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/target/linux/ath79/dts/ar7100.dtsi b/target/linux/ath79/dts/ar7100.dtsi
index 8994a7d688..6402657841 100644
--- a/target/linux/ath79/dts/ar7100.dtsi
+++ b/target/linux/ath79/dts/ar7100.dtsi
@@ -182,6 +182,7 @@
 
 	resets = <&rst 9>;
 	reset-names = "mac";
+	qca,mac-idx = <0>;
 };
 
 &mdio1 {
@@ -201,4 +202,5 @@
 
 	resets = <&rst 13>;
 	reset-names = "mac";
+	qca,mac-idx = <1>;
 };
diff --git a/target/linux/ath79/dts/ar9132.dtsi b/target/linux/ath79/dts/ar9132.dtsi
index 9d8ddcf9ba..2264994279 100644
--- a/target/linux/ath79/dts/ar9132.dtsi
+++ b/target/linux/ath79/dts/ar9132.dtsi
@@ -193,4 +193,5 @@
 	pll-handle = <&pll>;
 	resets = <&rst 9>;
 	reset-names = "mac";
+	qca,mac-idx = <0>;
 };
diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
index 1e0bb6937f..7f64a65817 100644
--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
+++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
@@ -529,6 +529,60 @@ static void ath79_set_pll(struct ag71xx *ag)
 	udelay(100);
 }
 
+static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
+{
+	u32 t;
+
+	t = __raw_readl(ag->mii_base);
+	t &= ~(AR71XX_MII_CTRL_IF_MASK);
+	t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
+	__raw_writel(t, ag->mii_base);
+}
+
+static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
+{
+	unsigned int mii_if;
+
+	switch (ag->phy_if_mode) {
+	case PHY_INTERFACE_MODE_MII:
+		mii_if = AR71XX_MII0_CTRL_IF_MII;
+		break;
+	case PHY_INTERFACE_MODE_GMII:
+		mii_if = AR71XX_MII0_CTRL_IF_GMII;
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+		mii_if = AR71XX_MII0_CTRL_IF_RGMII;
+		break;
+	case PHY_INTERFACE_MODE_RMII:
+		mii_if = AR71XX_MII0_CTRL_IF_RMII;
+		break;
+	default:
+		WARN(1, "Impossible PHY mode defined.\n");
+		return;
+	}
+
+	ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
+static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
+{
+	unsigned int mii_if;
+
+	switch (ag->phy_if_mode) {
+	case PHY_INTERFACE_MODE_RMII:
+		mii_if = AR71XX_MII1_CTRL_IF_RMII;
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+		mii_if = AR71XX_MII1_CTRL_IF_RGMII;
+		break;
+	default:
+		WARN(1, "Impossible PHY mode defined.\n");
+		return;
+	}
+
+	ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
 {
 	unsigned int mii_speed;
@@ -1272,7 +1326,7 @@ static int ag71xx_probe(struct platform_device *pdev)
 	struct resource *res;
 	struct ag71xx *ag;
 	const void *mac_addr;
-	u32 max_frame_len;
+	u32 max_frame_len, mac_idx;
 	int tx_size, err;
 
 	if (!np)
@@ -1427,6 +1481,14 @@ static int ag71xx_probe(struct platform_device *pdev)
 		goto err_free;
 	}
 
+	if ((ag->mii_base) &&
+		(!of_property_read_u32(np, "qca,mac-idx", &mac_idx))) {
+		if (mac_idx == 0)
+			ath79_mii0_ctrl_set_if(ag);
+		else if (mac_idx == 1)
+			ath79_mii1_ctrl_set_if(ag);
+	}
+
 	netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
 
 	ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
-- 
2.17.1


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