[PATCH v2 12/12] [NOT-FOR-UPSTREAM] platform: generic: Add sample dts overlays for testing hwirq/domain route rules
Raymond Mao
raymondmaoca at gmail.com
Thu Oct 29 08:59:29 PDT 2026
From: Raymond Mao <raymond.mao at riscstar.com>
Introduce rpmi_sysirq_intc nodes with interrupts-extended property
for VIRQ testing.
- Routing rules are derived from sysirq nodes by:
interrupts-extended =
<&aplic HWIRQx IRQ_TYPE>, // virq 0
<&aplic HWIRQy IRQ_TYPE>, // virq 1
...;
- VIRQ numbers are allocated from zero, implicit from the order
of the entries in the interrupts-extended property.
During cold boot, route rules are converted and cached for VIRQ
routing/couriering purpose, and DT IRQ entries activate courier delivery.
hwirq_bind_domain.dts is for testing with a single domain/hart.
Domain1 owns UART hwirq 10 via 'interrupts-extended'.
hwirq_bind_domain_linux_bmapp.dts is for testing with multiple
domains/harts. It models two BM domains alongside the root domain
on 'QEMU virt -smp 4'. Domain1 and domain2 share hart2 as boot hart
and each maps its own bm-app RAM region and the UART region;
domain2 owns UART hwirq 10 via 'interrupts-extended'.
Bind CPU hart2 to domain1 and set explicit init-order values to keep
hart2 in domain1 for initial execution. Load the BM payloads at
0x88000000 and 0x89000000 to exercise domain1 -> domain2 -> domain1.
Keep the configured courier sources 10, 20 and 21 in the M-mode APLIC
and delegate the remaining sources to its S-mode child. This preserves
Linux interrupt delivery without delegating the BM domains' IRQs.
Usage:
1. Compile the overlay.
$ dtc -@ -I dts -O dtb -o <dto_file> \
platform/generic/virt/<dts_overlay_file>
2. Dump the base dtb from QEMU via arg
'-machine dumpdtb=<dtb_qemu_base>'
3. Apply the overlay on the base.
$ fdtoverlay -i <dtb_qemu_base> -o <dtb_qemu_merge> <dto_file>
4. Re-run QEMU with adding argument '-dtb <dtb_qemu_merge>'
Signed-off-by: Raymond Mao <raymond.mao at riscstar.com>
---
platform/generic/virt/hwirq_bind_domain.dts | 107 +++++++++++++++
.../virt/hwirq_bind_domain_linux_bmapp.dts | 125 ++++++++++++++++++
2 files changed, 232 insertions(+)
create mode 100644 platform/generic/virt/hwirq_bind_domain.dts
create mode 100644 platform/generic/virt/hwirq_bind_domain_linux_bmapp.dts
diff --git a/platform/generic/virt/hwirq_bind_domain.dts b/platform/generic/virt/hwirq_bind_domain.dts
new file mode 100644
index 00000000..93f21d0b
--- /dev/null
+++ b/platform/generic/virt/hwirq_bind_domain.dts
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/dts-v1/;
+/plugin/;
+
+/ {
+ /*
+ * Fragment 0: OpenSBI domain configuration under /chosen
+ */
+ fragment at 0 {
+ target-path = "/chosen";
+ __overlay__ {
+ opensbi-domains {
+ compatible = "opensbi,domain,config";
+
+ /*
+ * DRAM region for domain1 (2GB from 0x8000_0000).
+ * base is 64-bit: <hi lo>, order is log2(size).
+ */
+ memregion_dram_2g: memregion_dram_2g {
+ compatible = "opensbi,domain,memregion";
+ base = <0x0 0x80000000>;
+ order = <31>;
+ };
+
+ /*
+ * UART MMIO region so S-mode payload can access UART registers
+ * without fault. 0x1000_0000 size 4KB.
+ */
+ uart0_mmio: memregion_uart0 {
+ compatible = "opensbi,domain,memregion";
+ base = <0x0 0x10000000>;
+ order = <12>;
+ };
+
+ /*
+ * Domain instance:
+ * - possible-harts = <cpu0 phandle> (cpu at 0 phandle is 1)
+ * - regions use label references (fdtoverlay will fixup phandles)
+ * - IRQ routing is defined by sysirq nodes under
+ * /chosen/opensbi-domains
+ */
+ domain1: domain1 {
+ compatible = "opensbi,domain,instance";
+
+ /* cpu at 0 phandle in base qemu dtb is 1 */
+ possible-harts = <0x1>;
+
+ /*
+ * Keep permissive for test.
+ * access=0x3f: enable all M+SU R/W/X flags (test only).
+ */
+ regions = <&memregion_dram_2g 0x3f>,
+ <&uart0_mmio 0x3f>;
+
+ /* Route rules are supplied via sysirq nodes. */
+ };
+
+ rpmi_sysirq_intc: interrupt-controller {
+ compatible = "opensbi,mpxy-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ /*
+ * VIRQ numbers are allocated from zero, in order.
+ * Each entry: <&irqchip hwirq flags>
+ * flags: IRQ_TYPE_LEVEL_HIGH = 4
+ */
+ /*
+ * Base DTB (qemu_linux_test.dtb) phandle:
+ * /soc/interrupt-controller at c000000 -> 0x09
+ */
+ interrupts-extended =
+ <0x09 10 4>, /* VIRQ 0: UART RX */
+ <0x09 20 4>, /* VIRQ 1: test */
+ <0x09 21 4>; /* VIRQ 2: test */
+
+ /* MPXY channel id allocated by system designer */
+ opensbi,mpxy-channel-id = <4>;
+
+ /* Route VIRQs to domain1 */
+ opensbi,domain = <&domain1>;
+ };
+ };
+ };
+ };
+
+ /*
+ * Fragment 1: Assign cpu0 to domain1 using label reference
+ */
+ fragment at 1 {
+ target-path = "/cpus/cpu at 0";
+ __overlay__ {
+ opensbi-domain = <&domain1>;
+ };
+ };
+
+ fragment at 2 {
+ target-path = "/soc/interrupt-controller at c000000";
+ __overlay__ {
+ /* Keep courier IRQs 10, 20 and 21 in the M-mode APLIC. */
+ riscv,delegate = <0x0a 1 9>, <0x0a 11 19>,
+ <0x0a 22 96>;
+ riscv,delegation = <0x0a 1 9>, <0x0a 11 19>,
+ <0x0a 22 96>;
+ };
+ };
+};
diff --git a/platform/generic/virt/hwirq_bind_domain_linux_bmapp.dts b/platform/generic/virt/hwirq_bind_domain_linux_bmapp.dts
new file mode 100644
index 00000000..d26e4237
--- /dev/null
+++ b/platform/generic/virt/hwirq_bind_domain_linux_bmapp.dts
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment at 0 {
+ target-path = "/chosen";
+ __overlay__ {
+ opensbi-domains {
+ compatible = "opensbi,domain,config";
+
+ d1_uart_mmio: memregion_domain1_uart_mmio {
+ compatible = "opensbi,domain,memregion";
+ base = <0x0 0x10000000>;
+ order = <12>;
+ mmio;
+ };
+
+ d1_bmapp_ram: memregion_domain1_bmapp_ram {
+ compatible = "opensbi,domain,memregion";
+ base = <0x0 0x88000000>;
+ order = <24>;
+ };
+
+ d2_bmapp_ram: memregion_domain2_bmapp_ram {
+ compatible = "opensbi,domain,memregion";
+ base = <0x0 0x89000000>;
+ order = <24>;
+ };
+
+ /*
+ * Domain instance:
+ * - possible-harts uses CPU node phandles
+ * - regions use label references (fdtoverlay will fixup phandles)
+ */
+ domain1: domain1 {
+ compatible = "opensbi,domain,instance";
+ init-order = <1>;
+
+ /*
+ * QEMU virt -smp 4 dumpdtb phandles:
+ * cpu at 1 -> 0x05, cpu at 2 -> 0x03
+ */
+ possible-harts = <0x05 0x03>;
+ boot-hart = <0x03>;
+
+ /*
+ * Keep permissive for test.
+ * access=0x3f: enable all M+SU R/W/X flags (test only).
+ */
+ regions = <&d1_bmapp_ram 0x3f>,
+ <&d1_uart_mmio 0x3f>;
+
+ next-addr = <0x0 0x88000000>;
+ next-arg1 = <0x0 0x1>;
+ next-mode = <0x1>;
+ };
+
+ domain2: domain2 {
+ compatible = "opensbi,domain,instance";
+ init-order = <2>;
+
+ /*
+ * QEMU virt -smp 4 dumpdtb phandles:
+ * cpu at 1 -> 0x05, cpu at 2 -> 0x03
+ */
+ possible-harts = <0x05 0x03>;
+ boot-hart = <0x03>;
+
+ regions = <&d2_bmapp_ram 0x3f>,
+ <&d1_uart_mmio 0x3f>;
+
+ next-addr = <0x0 0x89000000>;
+ next-arg1 = <0x0 0x2>;
+ next-mode = <0x1>;
+ };
+
+ rpmi_sysirq_intc: interrupt-controller {
+ compatible = "opensbi,mpxy-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ /*
+ * VIRQ numbers are allocated from zero, in order.
+ * Each entry: <&irqchip hwirq flags>
+ * flags: IRQ_TYPE_LEVEL_HIGH = 4
+ */
+ /*
+ * Base DTB (qemu_linux_test.dtb) phandle:
+ * /soc/interrupt-controller at c000000 -> 0x09
+ */
+ interrupts-extended =
+ <0x09 10 4>, /* VIRQ 0: UART RX */
+ <0x09 20 4>, /* VIRQ 1: test */
+ <0x09 21 4>; /* VIRQ 2: test */
+
+ /* MPXY channel id allocated by system designer */
+ opensbi,mpxy-channel-id = <4>;
+
+ /* Route VIRQs to domain2 */
+ opensbi,domain = <&domain2>;
+ };
+ };
+ };
+ };
+
+ fragment at 1 {
+ target-path = "/cpus/cpu at 2";
+ __overlay__ {
+ opensbi-domain = <&domain1>;
+ };
+ };
+
+ fragment at 2 {
+ target-path = "/soc/interrupt-controller at c000000";
+ __overlay__ {
+ /* Keep courier IRQs 10, 20 and 21 in the M-mode APLIC. */
+ riscv,delegate = <0x0a 1 9>, <0x0a 11 19>,
+ <0x0a 22 96>;
+ riscv,delegation = <0x0a 1 9>, <0x0a 11 19>,
+ <0x0a 22 96>;
+ };
+ };
+
+};
--
2.25.1
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