[PATCH v3 1/3] lib: sbi: Add RISC-V vector context save/restore support

[Radim Krcmar]

2026-03-27T17:15:59+00:00, <dave.patel at riscstar.com>:
> From: Dave Patel <dave.patel at riscstar.com>
>
> Eager context switch: Add support for saving and restoring RISC-V vector
> extension state in OpenSBI. This introduces a per-hart vector context
> structure and helper routines to perform full context save and restore.
>
> The vector context includes vl, vtype, vcsr CSRs along with storage for all
> 32 vector registers. The register state is saved and restored using byte-wise
> vector load/store instructions (vse8.v/vle8.v), making the implementation
> independent of current SEW/LMUL configuration.

Using the whole register store/load (vs8r/vl8r) is more appropriate.
We must manipulate the whole architectural register file regardless of
what is configured by lower privileged modes.

(I think vse/vle shouldn't be used for the purpose of context-switching
 as it's too easy to introduce a security issue with them.)

> The implementation follows an eager context switching model where the entire
> vector state is saved and restored on every context switch. This provides a
> simple and deterministic mechanism without requiring lazy trap-based
> management.

The code below uses the lower privilege's vl/vtype, which means that we
do not save the entire vector register file, but only the subset that is
currently configured by lower-privileges.  This creates a side-channel.

> Notes:
> - The SBI_MAX_VLENB is configured using CONFIG_SBI_MAX_VLENB.
>
> Signed-off-by: Dave Patel <dave.patel at riscstar.com>
> ---
> diff --git a/include/sbi/sbi_vector.h b/include/sbi/sbi_vector.h
[...]
> +	/* Restore CSRs first */
> +	WRITE_CSR(vtype,  src->vtype);
> +	WRITE_CSR(vl,     src->vl);

vl and vtype are read-only registers... how does this work?

Thanks.