[PATCH 1/4] lib: utils: irqchip: aplic: Move register defines to public header
David E. Garcia Porras
david.garcia at aheadcomputing.com
Fri Mar 27 22:43:44 PDT 2026
The APLIC register-level defines (DOMAINCFG, SOURCECFG, TARGET, SETIE,
CLRIE, IDC, MSICFG, etc.) are currently defined locally in aplic.c and
not accessible to platform code. Platform implementations that need
direct APLIC register access for custom interrupt configuration (e.g.
MSI-mode source/target setup) have no way to use the canonical defines.
Move these defines from aplic.c to the public aplic.h header so that
platform code can configure APLIC registers without duplicating magic
numbers. The defines match the RISC-V AIA specification. No functional
change.
Signed-off-by: David E. Garcia Porras <david.garcia at aheadcomputing.com>
---
include/sbi_utils/irqchip/aplic.h | 101 ++++++++++++++++++++++++++++++
lib/utils/irqchip/aplic.c | 101 ------------------------------
2 files changed, 101 insertions(+), 101 deletions(-)
diff --git a/include/sbi_utils/irqchip/aplic.h b/include/sbi_utils/irqchip/aplic.h
index 3461d1c7..286c8f94 100644
--- a/include/sbi_utils/irqchip/aplic.h
+++ b/include/sbi_utils/irqchip/aplic.h
@@ -14,6 +14,107 @@
#include <sbi/sbi_types.h>
#include <sbi/sbi_irqchip.h>
+#define APLIC_MAX_IDC (1UL << 14)
+#define APLIC_MAX_SOURCE 1024
+
+#define APLIC_DOMAINCFG 0x0000
+#define APLIC_DOMAINCFG_IE (1 << 8)
+#define APLIC_DOMAINCFG_DM (1 << 2)
+#define APLIC_DOMAINCFG_BE (1 << 0)
+
+#define APLIC_SOURCECFG_BASE 0x0004
+#define APLIC_SOURCECFG_D (1 << 10)
+#define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
+#define APLIC_SOURCECFG_SM_MASK 0x00000007
+#define APLIC_SOURCECFG_SM_INACTIVE 0x0
+#define APLIC_SOURCECFG_SM_DETACH 0x1
+#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
+#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
+#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6
+#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7
+
+#define APLIC_MMSICFGADDR 0x1bc0
+#define APLIC_MMSICFGADDRH 0x1bc4
+#define APLIC_SMSICFGADDR 0x1bc8
+#define APLIC_SMSICFGADDRH 0x1bcc
+
+#define APLIC_xMSICFGADDRH_L (1UL << 31)
+#define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f
+#define APLIC_xMSICFGADDRH_HHXS_SHIFT 24
+#define APLIC_xMSICFGADDRH_LHXS_MASK 0x7
+#define APLIC_xMSICFGADDRH_LHXS_SHIFT 20
+#define APLIC_xMSICFGADDRH_HHXW_MASK 0x7
+#define APLIC_xMSICFGADDRH_HHXW_SHIFT 16
+#define APLIC_xMSICFGADDRH_LHXW_MASK 0xf
+#define APLIC_xMSICFGADDRH_LHXW_SHIFT 12
+#define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff
+
+#define APLIC_xMSICFGADDR_PPN_SHIFT 12
+
+#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \
+ ((1UL << (__lhxs)) - 1)
+
+#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \
+ ((1UL << (__lhxw)) - 1)
+#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \
+ ((__lhxs))
+#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \
+ (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \
+ APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs))
+
+#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \
+ ((1UL << (__hhxw)) - 1)
+#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \
+ ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT)
+#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \
+ (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \
+ APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs))
+
+#define APLIC_SETIP_BASE 0x1c00
+#define APLIC_SETIPNUM 0x1cdc
+
+#define APLIC_CLRIP_BASE 0x1d00
+#define APLIC_CLRIPNUM 0x1ddc
+
+#define APLIC_SETIE_BASE 0x1e00
+#define APLIC_SETIENUM 0x1edc
+
+#define APLIC_CLRIE_BASE 0x1f00
+#define APLIC_CLRIENUM 0x1fdc
+
+#define APLIC_SETIPNUM_LE 0x2000
+#define APLIC_SETIPNUM_BE 0x2004
+
+#define APLIC_TARGET_BASE 0x3004
+#define APLIC_TARGET_HART_IDX_SHIFT 18
+#define APLIC_TARGET_HART_IDX_MASK 0x3fff
+#define APLIC_TARGET_GUEST_IDX_SHIFT 12
+#define APLIC_TARGET_GUEST_IDX_MASK 0x3f
+#define APLIC_TARGET_IPRIO_MASK 0xff
+#define APLIC_TARGET_EIID_MASK 0x7ff
+
+#define APLIC_IDC_BASE 0x4000
+#define APLIC_IDC_SIZE 32
+
+#define APLIC_IDC_IDELIVERY 0x00
+
+#define APLIC_IDC_IFORCE 0x04
+
+#define APLIC_IDC_ITHRESHOLD 0x08
+
+#define APLIC_IDC_TOPI 0x18
+#define APLIC_IDC_TOPI_ID_SHIFT 16
+#define APLIC_IDC_TOPI_ID_MASK 0x3ff
+#define APLIC_IDC_TOPI_PRIO_MASK 0xff
+
+#define APLIC_IDC_CLAIMI 0x1c
+
+#define APLIC_DEFAULT_PRIORITY 1
+#define APLIC_DISABLE_IDELIVERY 0
+#define APLIC_ENABLE_IDELIVERY 1
+#define APLIC_DISABLE_ITHRESHOLD 1
+#define APLIC_ENABLE_ITHRESHOLD 0
+
#define APLIC_MAX_DELEGATE 16
struct aplic_msicfg_data {
diff --git a/lib/utils/irqchip/aplic.c b/lib/utils/irqchip/aplic.c
index ec69c82b..a20cecf2 100644
--- a/lib/utils/irqchip/aplic.c
+++ b/lib/utils/irqchip/aplic.c
@@ -14,107 +14,6 @@
#include <sbi/sbi_error.h>
#include <sbi_utils/irqchip/aplic.h>
-#define APLIC_MAX_IDC (1UL << 14)
-#define APLIC_MAX_SOURCE 1024
-
-#define APLIC_DOMAINCFG 0x0000
-#define APLIC_DOMAINCFG_IE (1 << 8)
-#define APLIC_DOMAINCFG_DM (1 << 2)
-#define APLIC_DOMAINCFG_BE (1 << 0)
-
-#define APLIC_SOURCECFG_BASE 0x0004
-#define APLIC_SOURCECFG_D (1 << 10)
-#define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
-#define APLIC_SOURCECFG_SM_MASK 0x00000007
-#define APLIC_SOURCECFG_SM_INACTIVE 0x0
-#define APLIC_SOURCECFG_SM_DETACH 0x1
-#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
-#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
-#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6
-#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7
-
-#define APLIC_MMSICFGADDR 0x1bc0
-#define APLIC_MMSICFGADDRH 0x1bc4
-#define APLIC_SMSICFGADDR 0x1bc8
-#define APLIC_SMSICFGADDRH 0x1bcc
-
-#define APLIC_xMSICFGADDRH_L (1UL << 31)
-#define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f
-#define APLIC_xMSICFGADDRH_HHXS_SHIFT 24
-#define APLIC_xMSICFGADDRH_LHXS_MASK 0x7
-#define APLIC_xMSICFGADDRH_LHXS_SHIFT 20
-#define APLIC_xMSICFGADDRH_HHXW_MASK 0x7
-#define APLIC_xMSICFGADDRH_HHXW_SHIFT 16
-#define APLIC_xMSICFGADDRH_LHXW_MASK 0xf
-#define APLIC_xMSICFGADDRH_LHXW_SHIFT 12
-#define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff
-
-#define APLIC_xMSICFGADDR_PPN_SHIFT 12
-
-#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \
- ((1UL << (__lhxs)) - 1)
-
-#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \
- ((1UL << (__lhxw)) - 1)
-#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \
- ((__lhxs))
-#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \
- (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \
- APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs))
-
-#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \
- ((1UL << (__hhxw)) - 1)
-#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \
- ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT)
-#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \
- (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \
- APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs))
-
-#define APLIC_SETIP_BASE 0x1c00
-#define APLIC_SETIPNUM 0x1cdc
-
-#define APLIC_CLRIP_BASE 0x1d00
-#define APLIC_CLRIPNUM 0x1ddc
-
-#define APLIC_SETIE_BASE 0x1e00
-#define APLIC_SETIENUM 0x1edc
-
-#define APLIC_CLRIE_BASE 0x1f00
-#define APLIC_CLRIENUM 0x1fdc
-
-#define APLIC_SETIPNUM_LE 0x2000
-#define APLIC_SETIPNUM_BE 0x2004
-
-#define APLIC_TARGET_BASE 0x3004
-#define APLIC_TARGET_HART_IDX_SHIFT 18
-#define APLIC_TARGET_HART_IDX_MASK 0x3fff
-#define APLIC_TARGET_GUEST_IDX_SHIFT 12
-#define APLIC_TARGET_GUEST_IDX_MASK 0x3f
-#define APLIC_TARGET_IPRIO_MASK 0xff
-#define APLIC_TARGET_EIID_MASK 0x7ff
-
-#define APLIC_IDC_BASE 0x4000
-#define APLIC_IDC_SIZE 32
-
-#define APLIC_IDC_IDELIVERY 0x00
-
-#define APLIC_IDC_IFORCE 0x04
-
-#define APLIC_IDC_ITHRESHOLD 0x08
-
-#define APLIC_IDC_TOPI 0x18
-#define APLIC_IDC_TOPI_ID_SHIFT 16
-#define APLIC_IDC_TOPI_ID_MASK 0x3ff
-#define APLIC_IDC_TOPI_PRIO_MASK 0xff
-
-#define APLIC_IDC_CLAIMI 0x1c
-
-#define APLIC_DEFAULT_PRIORITY 1
-#define APLIC_DISABLE_IDELIVERY 0
-#define APLIC_ENABLE_IDELIVERY 1
-#define APLIC_DISABLE_ITHRESHOLD 1
-#define APLIC_ENABLE_ITHRESHOLD 0
-
static SBI_LIST_HEAD(aplic_list);
static void aplic_writel_msicfg(struct aplic_msicfg_data *msicfg,
void *msicfgaddr, void *msicfgaddrH);
--
2.43.0
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