[PATCH 1/3] lib: sbi: Add Smrnmi extension detection

Anup Patel anup at brainfault.org
Sat Mar 7 20:27:38 PST 2026


On Thu, Jan 29, 2026 at 1:44 PM Nylon Chen <nylon.chen at sifive.com> wrote:
>
> Add detection support for the RISC-V Smrnmi (Resumable Non-Maskable
> Interrupts) extension.
>
> Co-developed-by: Zong Li <zong.li at sifive.com>
> Signed-off-by: Zong Li <zong.li at sifive.com>
> Suggested-by: Nick Hu <nick.hu at sifive.com>
> Signed-off-by: Nylon Chen <nylon.chen at sifive.com>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang at sifive.com>
> ---
>  include/sbi/riscv_encoding.h | 11 +++++++++++
>  include/sbi/sbi_hart.h       |  2 ++
>  lib/sbi/sbi_hart.c           |  1 +
>  3 files changed, 14 insertions(+)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index b5a4ce81..eb556380 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -215,6 +215,11 @@
>
>  #endif
>
> +/* Smrnmi extension status bits */
> +#define MNSTATUS_NMIE                  (_UL(0x8))
> +#define MNSTATUS_MNPV                  (_UL(0x80))
> +#define MNSTATUS_MNPP                  (_UL(0x1800))

Please add define fo mnstatus.MNPELP bit as well.

> +
>  #define MHPMEVENT_SSCOF_MASK           _ULL(0xFF00000000000000)
>
>  #define ENVCFG_STCE                    (_ULL(1) << 63)
> @@ -780,6 +785,12 @@
>  #define CSR_MVIPH                      0x319
>  #define CSR_MIPH                       0x354
>
> +/* Smrnmi extension registers */
> +#define CSR_MNSCRATCH                  0x740
> +#define CSR_MNEPC                      0x741
> +#define CSR_MNCAUSE                    0x742
> +#define CSR_MNSTATUS                   0x744
> +
>  /* Vector extension registers */
>  #define CSR_VSTART                     0x8
>  #define CSR_VL                         0xc20
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index a788b34c..7d038a18 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -87,6 +87,8 @@ enum sbi_hart_extensions {
>         SBI_HART_EXT_XSIFIVE_CFLUSH_D_L1,
>         /** Hart has Xsfcease extension */
>         SBI_HART_EXT_XSIFIVE_CEASE,
> +       /** HART has Smrnmi extension **/
> +       SBI_HART_EXT_SMRNMI,
>
>         /** Maximum index of Hart extension */
>         SBI_HART_EXT_MAX,
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 60e95bca..495ad1d8 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -396,6 +396,7 @@ const struct sbi_hart_ext_data sbi_hart_ext[] = {
>         __SBI_HART_EXT_DATA(ssstateen, SBI_HART_EXT_SSSTATEEN),
>         __SBI_HART_EXT_DATA(xsfcflushdlone, SBI_HART_EXT_XSIFIVE_CFLUSH_D_L1),
>         __SBI_HART_EXT_DATA(xsfcease, SBI_HART_EXT_XSIFIVE_CEASE),
> +       __SBI_HART_EXT_DATA(smrnmi, SBI_HART_EXT_SMRNMI),
>  };
>
>  _Static_assert(SBI_HART_EXT_MAX == array_size(sbi_hart_ext),
>
> --
> 2.43.7
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

Otherwise, LGTM.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup



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