[PATCH v5 0/6] ISC-V AIA: APLIC and IMSIC irqchip framework integration

[Anup Patel]

On Wed, Jul 22, 2026 at 3:19 AM Pawandeep Oza
<pawandeep.oza at oss.qualcomm.com> wrote:
>
> From: Oza Pawandeep <pawandeep.oza at oss.qualcomm.com>
>
> This series integrates the RISC-V Advanced Interrupt Architecture (AIA)
> APLIC and IMSIC M-mode drivers into the OpenSBI sbi_irqchip framework,
> replacing the previous standalone experimental driver with a complete
> callback-based implementation.
>
> The series adds full support for:
>
>   - APLIC Direct Mode (IDC) interrupt delivery with per-hart IDC
>     register management, priority-based routing, and source delegation
>     to S-mode child domains.
>
>   - APLIC MSI Mode fallback where IDC structures are absent, routing
>     wired interrupts through IMSIC by programming APLIC TARGET registers
>     with hart index, guest index, and dynamically allocated EIIDs.
>
>   - IMSIC instance-based irqchip registration with per-hart interrupt
>     file management, EIE CSR state tracking, warm-boot state restoration,
>     and MSI composition for upstream APLIC affinity reprogramming.
>
>   - A decoupled architecture between APLIC and IMSIC drivers mediated
>     by the sbi_irqchip framework. APLIC registers write_msi and
>     msi_callback hooks; IMSIC registers the irqchip MSI sink. Neither
>     driver directly references the other's data structures.
>
>   - IRQ enable state tracking in the irqchip framework via a new
>     irq_state field and IRQ_ENABLED flag, exposed through
>     sbi_irqchip_is_irq_enabled() for warm-boot EIE CSR restoration.
>
>   - A fix for two allocation bugs in sbi_irqchip_register_msi() that
>     prevented contiguous EIID allocation when reserved handlers were
>     already registered.
>
> Driver initialization follows hardware dependency ordering:
>
>   IMSIC cold init → APLIC cold init
>
> The IMSIC irqchip must be registered before APLIC so that APLIC MSI
> mode can resolve the parent chip by unique_id via
> sbi_irqchip_find_device() during hwirq_setup.
>
> APLIC Direct Mode and MSI Mode are mutually exclusive and selected
> at cold init time based on the presence of IDC structures (num_idc)
> and the IMSIC geometry (has_msicfg_mmode) parsed from the Device Tree.
>
> Testing was performed on a QEMU RISC-V platform with 128 harts, two
> APLIC domains (M-mode at 0x10010000, S-mode at 0x10018000), and two
> IMSIC instances (Hart 0-1 at 0x19e0000, Hart 2-3 at 0x19f0000) with
> 31 wired interrupt sources. End-to-end M-mode interrupt delivery via
> APLIC MSI mode was verified using a software interrupt test client
> exercising the GENMSI path.
>
> Changes since v1:
> APLIC MSI Decoding:
> Refactored the hart_index derivation logic in derive_hart_index()
> to use Page Frame Number (PPN) based shifts and masks.
>
> Changes since v2:
> Added SBI_EALREADY guard to fail if hwirq was already unmasked
> aplic_hwirq_eoi handles only msi mode for aplic
> aplic_process_irq now reads APLIC_IDC_CLAIMI
>
> Changes since v3:
> print formatting corrected
> removed aplic_msi_ptrs[] and added sbi_irqchip_get_handler_priv helper
> renamed sbi_irqchip_is_irq_enabled to sbi_irqchip_is_hwirq_enabled
>
> Changes since v4:
> -----------------
> * Replaced sbi_irqchip_get_handler_priv() with a generic per-hwirq
>   private data API. Added "void *priv" field to struct
>   sbi_irqchip_hwirq_data and introduced sbi_irqchip_set_hwirq_priv()
>   and sbi_irqchip_get_hwirq_priv() to set and retrieve per-hwirq
>   private data. The API is no longer typed to struct aplic_msi_data
>   and is now fully generic.
>
> * Dropped parent_irq_map[] from struct aplic_data. The EIID-to-source
>   mapping is now tracked via the per-hwirq private data. Added
>   parent_hwirq field to struct aplic_msi_data to record the IMSIC
>   hwirq allocated for each APLIC source. hwirq_setup stores this via
>   sbi_irqchip_set_hwirq_priv() and hwirq_set_affinity retrieves it
>   via sbi_irqchip_get_hwirq_priv().
>
> * Fixed APLIC MSI-mode EOI for level-triggered interrupts. Replaced
>   aplic_irq_clrip() with a write to SETIPNUM to re-trigger the
>   interrupt pending state, aligning with the Linux APLIC MSI-mode
>   driver behaviour (irq-riscv-aplic-msi.c, aplic_ipi_send_mask()).
>
> * Fixed tab/space alignment issues throughout aplic.c and
>   sbi_irqchip.c.
>
> * Replaced all hard-coded function name strings in sbi_printf() calls
>   with %s and __func__ across both the APLIC and IMSIC drivers.
>
> Pawandeep Oza (6):
>   lib: utils/irqchip/aplic: implement direct mode irqchip callbacks
>   lib: utils/irqchip/aplic: add MSI mode support with IMSIC parent
>     linking
>   lib: utils/irqchip/imsic: embed sbi_irqchip_device in imsic data
>   lib: utils/irqchip/imsic:migrate to irqchip framework
>   lib: utils/irqchip/imsic: track IRQ enable state and restore EIE on
>     warm init
>   lib: sbi_irqchip: fix MSI EIID gap and tail allocation logic in
>     register_msi
>
>  include/sbi/sbi_irqchip.h         |  10 +
>  include/sbi_utils/irqchip/aplic.h |   1 +
>  include/sbi_utils/irqchip/imsic.h |   2 +
>  lib/sbi/sbi_irqchip.c             |  74 +++-
>  lib/utils/fdt/fdt_helper.c        |   1 +
>  lib/utils/irqchip/aplic.c         | 560 +++++++++++++++++++++++++++---
>  lib/utils/irqchip/imsic.c         | 308 +++++++++++++---
>  7 files changed, 861 insertions(+), 95 deletions(-)
>
> --
> 2.43.0
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

Applied this series to the riscv/opensbi repo.

Thanks,
Anup